Complementary FET (CFET) is a promising device architecture that proceeds the CMOS scaling during the post-nanosheet device era. Among several CFET variants, Double-Row (DR) CFET further enables 15% track height scaling on standard cells, by sharing a middle row of vias, while sustaining an optimized Middle-Of-Line (MOL) process complexity. In this study, half-height double-row (hDR) CFET is proposed as a highly practical and impactful design style to overcome the cell and block level limitations of DR CFET architecture. First, hDR CFET introduces a high flexibility on standard cell layout design with significant area optimization. Secondly, hDR cell insertion in the backend physical design flow further optimizes the cell placement, and recovers block level area scaling to match the cell height scaling. Results on A7 CFET technology library show area reduction up to 50% on standard cell layouts. Moreover, block level PnR results after enabling only 6 types of hDR cells in standard cell library show 10% of area scaling on ARM Cortex-M0 32-bit core at 90% utilization, proving the strength of the concept. Finally, 14% of block level area scaling is further projected for an enriched standard cell library with an extended set of hDR cells.

The back-side metal layers exhibit lower parasitics compared to the front-side layers in advanced technologies, making them suitable for clock-net distribution. In this study, we explore the advantages of using back-side metal layers for clock routing, which is shared with a power delivery network. Our Graph Neural Network (GNN) based framework, effectively distributes the clock-tree between the front and back sides. We address the back-side clock nets' creation by incorporating back-side buffers. Our results demonstrate better clock and full-chip metrics represented by an increase of up to 13% in the effective frequency with equivalent power consumption, using 3 nm technology.

In sub 10 nm nodes, the growing dominance of interconnects in chips poses challenges in designing large-size static random-access memory (SRAM) subarrays. The main issue is the write failure problem arising from the increased resistance and capacitance for bitline (BL) and wordline (WL). To tackle this issue, the SRAM subarray design incorporates conventional (Conv.) divided WL and divided BL techniques based on 14-Å-compatible (A14) nanosheet (NS) technology. This approach allows for various subarray sizes with successful write operations, resulting in improved subarray-level performance and power (PP). However, the additional logic gates come with an area penalty that may degrade the overall performance, power, and area (PPA) at the macro level due to increased inter-subarray interconnect overhead. To overcome this limitation, the active interconnect (AIC) design is proposed with the features of fabricating another or multiple active regions at the back-end of line (BEOL) layers. By moving these extra logic gates from front-end of line to BEOL in the AIC divided subarray design, the area penalty is significantly mitigated without compromising PP compared to the standard (Std.) and Conv. divided counterparts. To achieve this concept, carbon nanotube gate-all-around transistor is explored as potential BEOL-compatible device. In this research, a comprehensive design-technology co-optimization analysis is conducted to verify the value and potential benefits of up to 65% macro-level energy-delay-area product improvement by AIC divided subarray design compared to the Std. subarray design.

In this paper, we introduce a novel design of a 3D static random-access memory (SRAM) macro in a 3D Nanofabric process technology. The 3D Nanofabric technology is based on enabling the processing of N stack of identical layers simultaneously regardless of the number of stacked layers which consequently reduces the fabrication cost as well as the footprint of SRAM macros. To enable simultaneous patterning of stacked layers, 3D Nanofabric requires circuit topology and layout that rely on a single layer where the device channel, poly, and metal wires are all embedded without any other crossing than the gate on top of the device channel. Accordingly, we modify the layouts of the conventional SRAM bit-cell and periphery circuits which are complex and contain several metal crossings. Furthermore, we propose a new overall organization of the 3D SRAM macro that incorporates a stack of multiple identical layers each consisting of an equal size 2D array of bit-cells and the periphery circuits. We show that the proposed 3D Nanofabric SRAM macro offers 71.2% footprint gain and 36.3% read access speed improvement compared to equal size 2D SRAM macro in 3 nm FinFET.

In this article, we provide a comprehensive evaluation of width modulation capabilities of both nanosheet (NS) and forksheet (FS) devices, going from device level to a block level implementation. The main innovation introduced by the FS consists of a dielectric wall added between the p- and nMOS transistors. Leveraging this feature, FS shows approximately the same current behavior as NS, considered a state-of-the-art reference, but reduced parasitic capacitance thanks to its fewer but wider stacked sheets. At block level, an area reduction up to 12% is observed with FS, alongside a 13% power reduction and 10% frequency increase. Following the device comparison, the potential of sheet width modulation as additional power, performance, and area (PPA) optimization technique during synthesis and place and route (PNR) is investigated. A description of the specific steps required to enable this knob in a conventional electronic design automation (EDA) framework is provided. As demonstrated by the obtained experimental results, the same frequency of the single-width implementation can be achieved using mixed libraries with lower power consumption (13% and 16% for NS and FS, respectively), leading to improved energy efficiency. Furthermore, it is shown how designs implemented using FS benefit more from this type of optimization than the ones using NS, with a 12%–15% energy reduction compared to the 8.5%–14% obtained with NS.