This paper presents a systematic study on developing multi-template machine learning (ML) surrogate models and applying them to the inverse design of transformers (XFMRs) in radio-frequency integrated circuits (RFICs). Our study starts with benchmarking four widely used ML architectures, including MLP-, CNN-, UNet-, and GT-based models, using the same datasets across different XFMR topologies. To improve modeling accuracy beyond these baselines, we then propose a new frequency-domain self-transfer learning technique that exploits correlations between adjacent frequency bands, leading to $\sim 30 \%-50 \%$ accuracy improvement in the S-parameters prediction. Building on these models, we further develop an inverse design framework based on the covariance matrix adaptation evolutionary strategy (CMA-ES) algorithm. This framework is validated using multiple impedance-matching tasks, all demonstrating fast convergence and trustworthy performance. These results advance the goal of AI-assisted “specs-to-GDS” automation for RFICs and provide RFIC designers with actionable tools for integrating AI into their workflows.

While AI for EDA has seen great success in digital IC design and some success in analog design, its potential for enabling RFIC design is yet to be fully explored. Due to its high-frequency nature, RFIC involves challenges such as parasitic effects, electromagnetic interference (EMI), signal integrity (SI), and other non-idealities. The modeling of passive networks and the associated computationally expensive EM simulations remain the major bottleneck in manual RFIC designs. This paper discusses the challenges and opportunities in ML-assisted RFIC design, covering topics from physics-augmented surrogate modeling to the inverse design of passive structures.

This paper presents how we leverage AI-human collaboration to develop an end-to-end, automated design flow for digitally controlled oscillators (DCOs), a key radio-frequency (RF) integrated circuits (ICs) building block that dominates phase noise and jitter performance of RF systems. Specifically, we decompose the DCO design process into two steps and use AI to enhance productivity and optimize performance within each step. Additionally, we demonstrate how AI can assist RF IC designers in creating unconventional circuit components to tackle challenging design specifications. Overall, the proposed flow is capable of synthesizing the DCO design including the schematic and layout in 80 seconds after one-time training, and is frequency agile between 1 and 20 GHz. Moreover, it can select the most robust design under process variations when multiple design parameters meet target specifications under the nominal condition. The proposed automated DCO design flow is demonstrated using two silicon prototypes implemented in the GlobalFoundries $22-\mathrm{nm}$ CMOS SOI process. In the measurements, they achieve $\gt 192.4-\mathrm{dBc} / \mathrm{Hz}$ figure-of-merit (FoM) and $\lt 1.5-\mathrm{kHz}$ frequency resolution at 7.1 to 8.6 GHz and 3.8 to 4.6 GHz, outperforming existing manual designs at similar frequencies.

The front-end synthesis of analog circuits has been a long-standing challenge since the advent of integrated circuits. Many methods, ranging from conventional optimization-based techniques to emerging learning-based approaches, have been extensively explored to address this challenge. Yet, these methods are data-driven and often suffer from low design efficiency, due to their heavy reliance on time-consuming circuit simulators, which are frequently used in the synthesis loop for real-time evaluation of the evolving circuit design. In addition, benchmarking these methods is also largely unachievable due to their exclusive use of commercial semiconductor technology for evaluation. This “Late Breaking Results” introduces Opera, an open and efficient platform for the data-driven synthesis of analog circuits. Specifically, Opera develops efficient surrogate models for various circuits and integrates them into open-source OpenAI Gym-like environments to enable efficient synthesis. Case studies on exemplary circuits show that this platform can accelerate the conventional data-driven synthesis flow by up to $40 \times$. It also enables the benchmarking of various synthesis methods with standardized environments built upon an open-source semiconductor process.

The exponential growth of information and computational workloads has created unprecedented demands for high-productivity development of computer hardware built on foundational semiconductor integrated circuits (ICs). Yet, the lack of effective design automation techniques makes developing analog ICs–indispensable in ubiquitous computer systems–a significant bottleneck for overall design productivity and cost efficiency across the IC ecosystem. Excitingly, recent advances in generative AI present transformative opportunities to tackle the complexity and large-scale challenges of modern analog/radio-frequency (RF) IC design. This work introduces a first-of-its-kind multi-agent generative synthesis framework for analog/RF circuits. Specifically, our approach formulates analog synthesis as a multi-stage generative AI problem: first generating a novel topology conditioned on high-level textual descriptions, and then producing high-quality device parameters to meet given design specifications for the generated circuit topology. This novel paradigm offers distinct advantages over traditional methods, including controllable novelty in topology generation and significantly improved inverse design efficiency. Beyond topology generation and inverse design, our method enables broader applications such as synthetic dataset generation and privacy-preserving data sharing–emerging challenges in data-driven electronic design automation (EDA) due to the computationally intensive and confidential nature of analog/RF circuit design. This work paves the way for next-generation generative AI-driven multi-agent synthesis in analog/RF EDA.

Securing low-power Internet-of- Things (IoT) sensor nodes presents a critical challenge for the widespread adoption of IoT technology, given their inherent limitations in energy, computation, and storage resources. As a promising alternative to conventional wireless security approaches based on cryptography, there has been a growing interest in RF physical-layer security, especially RF fingerprinting, which offers the promise of reduced overhead and energy consumption. In this work, we present an artificial neural network (ANN) model tailored to identify IoT transmitters by harnessing their unique power spectral density (PSD). The network is designed to be lightweight and can be readily implemented on resource-constrained IoT nodes. Combined with our customized radio frontend, we achieve superior identification performance. In the measurements, we can reliably identify 240 devices with a 99 % accuracy on trained distances and 40 devices with an above 95 % accuracy at an unknown distance that is excluded from the training data. These results demonstrate significant improvement in robustness, reliability, and identification accuracy over prior art while ensuring compatibility with resource-constrained IoT nodes.

This paper presents a design methodology that can effectively extend the bandwidth of a cascode common-source with inductive degeneration low noise amplifier (LNA), which is one of the most popular LNA topologies in the millimeter-wave bands. Specifically, this methodology addresses how to broaden the input matching bandwidth by realizing dual-resonant${S}$11, and how to extend the gain bandwidth by synthesizing a transformer-based second-order bandpass output network. As a proof of concept, a 27–46 GHz LNA is implemented in the GlobalFoundries 45-nm CMOS SOI process, achieving 25.5–50 GHz 3-dB gain bandwidth, 27–46 GHz return loss bandwidth, 21.2 dB peak gain, 2.4 dB minimum noise figure, and −9.5 dBm peak IIP 3, under 25.5 mW DC power consumption. Consistent performance is measured across multiple samples, demonstrating the robustness of the presented design methodology.