This article presents a systematic approach to generate layouts for two devices, with an arbitrary integer ratio of device sizes, that cancels up to at least third-order gradient effects. A new analysis leads to mathematical constraints on 1-D layouts that meet the required integer ratio and cancel second-order gradients. From those layouts, we apply reflection and rotation symmetries to generate 2-D layouts that cancel higher-order gradients. We demonstrate our proposed methodology on current sense transistors interspersed in active power transistors. Legato electrothermal simulation show our proposed approach, respectively, improves worst-case matching accuracy about a factor of 9.9 and 7.15 when compared to a common centroid (CC) and interdigitated (ID) pattern in the presence of gradients effects. Furthermore, we discuss evaluation metrics that can be used to select one of multiple gradient canceling layouts for any fixed rectangular grid and device application.

This article presents two improvements to, and a warning about a previously unrecognized issue with, statistical modeling, characterization, and simulation. We focus on mismatch, which is key for analog IC design, but the topics addressed are generic. For relative variation (i.e., % difference), we show that conventional measures have significant issues when the variation is large. We present two new measures of % difference between$y_{2}$and$y_{1}$and show that$100 \cdot {\mathrm {ln}} (y_{2} / y_{1})$is the only measure that is physically correct for mismatch. We review existing, but not widely known, robust alternatives to the textbook approach to estimate standard deviation, show the limitations of these, and propose a new method that is intermediate between, and overcomes limitations of, the textbook and robust approaches. We then show how the accuracy of mismatch simulation, critical for analog IC design, is affected by “spurious correlation” between statistical samples; we are not aware that the importance of this has been recognized previously.

On-chip testing for analog/mixed signal circuits helps improve reliability of safety-critical systems by enabling infield testing. It also alleviates the problems of increasing test costs. A low-cost high accuracy stimulus generator for on-chip spectral testing is proposed. The generator uses a low-cost DAC which requires minimal design and re-engineering efforts, in conjunction with INL based digital pre-distortion to calibrate its linearity performance. DAC output measurement, DAC INL estimation and DAC linearity calibration are all performed on-chip. Measurement results in 40nm bulk CMOS technology demonstrate that the circuit is capable of producing a rail-to-rail differential signal with THD of -75 dB and SFDR of 79dB. The proposed solution is a major step forward in demonstrating the feasibility of synthesizable built-in-test solutions for high-accuracy embedded analog and mixed signal functions.

This paper presents a complete on-chip ADC BIST solution based on a segmented stimulus error identification algorithm known as USER-SMILE. By adapting the algorithm for efficient hardware realization, the solution is implemented towards a 1Msps 12-bit SAR ADC on a 28nm CMOS automotive microcontroller. While sufficient test accuracy is demonstrated, the solution is further extended to correct linearity errors of ADC. The entire BIST and calibration circuitry occupies 0.028mm2silicon area while enabling more than 10 times tester time reduction and >10dB THD/SFDR performance improvement over an existing structural capacitor-weight-identification calibration scheme. The added die cost is estimated to be 1/8 of the saved test cost from tester time reduction alone.