EDBT 2026 Demo / reviewers in the wild / expert
Muhammad Asfandyar Awan
dblp:137/2837
· DBLP profile ↗
4ranked-venue papers
2as first author
3since 2021 · last 2026
0000-0003-2464-0523ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author · 3 since 2021Computer networks · 1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | A 4 nW 114 dB DR Electrochemical Sensing Interface IC with Digital-Intensive Regulation LoopabstractThis paper introduces an ultra-low-power amplifier-less front-end architecture for amperometric electrochemical sensing. The proposed architecture can simultaneously regulate the potential difference between the required electrodes and perform current readout for an electrochemical sensor. A dual-side potentiostat regulation loop comprising dynamic latched comparators in conjunction with digital loop filters and current-steering DACs is proposed, with its detailed operation discussed in this paper. Implemented in a standard 180 nm CMOS process, this design achieves a current measurement range of 114.3 dB. It can operate over a wide range of sampling frequencies FS (100 Hz ~ 100 MHz) and supply voltages (1 V ~ 1.8 V). The whole interface IC consumes only 3.50 nA current at 1.2 V supply at a clock frequency of 1-kHz. Muhammad Asfandyar Awan, Muhammad Haris Farooq, Amine Bermak, Muhammad Abrar Akram, Bo Wang 0012 |
ISCAS | 1 |
| 2025 | Current-Mirror Based Ambient Light Rejection Technique for VLC ReceiverabstractAmbient light interference is a significant hurdle as it creates unwanted DC current in optical receivers used for visible light communication, infrared communication, etc., that face solar irradiance in the daytime or unwanted light sources such as bulbs at night. This paper presents a current mirror-based receiver topology. By introducing a current-to-voltage converter module, the receiver can handily remove the background interference. A prototype receiver is designed using a 180 nm CMOS process operating at a speed of 160 MHz. It can cancel up to 100 µA of DC background interference while maintaining a low power dissipation of 7 mW from a 1.8 V supply. Additionally, it achieves a transimpedance gain of 120 dBΩ and an input referred noise of 10 pA/ Hz. Nasir Abdul Quadir, Muhammad Asfandyar Awan, Bo Wang 0012, Amine Bermak |
ISCAS | 2 |
| 2021 | Review and Analysis of CMOS Current Readout Circuits for Biosensing ApplicationsabstractCMOS current readout is a critical circuit block for various applications like bio-sensing. This paper presents an overview of CMOS current readout techniques and analyze their merits and demerits, including noise floor, sensitivity, and achievable system bandwidth. Mainly, the practical applicability of individual technique/design for integrated low-noise bio-sensing applications is discussed. To present a thorough insight of the state-of-the-art, most recent and relevant articles published in the literature related to the current sensing interface are summarized and compared. The paper identified the primary DC current rejection schemes, where each approach and its limitations are discussed and shown that each system comes with its limits. Muhammad Asfandyar Awan, Bo Wang 0012, Nasir Abdul Quadir, Amine Bermak |
ISCAS | 1 |
| 2020 | On the Performance of Wireless Video Communication Using Iterative Joint Source Channel Decoding and Transmitter Diversity Gain TechniqueabstractIn this research work, we have presented an iterative joint source channel decoding- (IJSCD-) based wireless video communication system. The anticipated transmission system is using the sphere packing (SP) modulation assisted differential space-time spreading (DSTS) multiple input-multiple output (MIMO) scheme. SP modulation-aided DSTS transmission mechanism results in achieving high diversity gain by keeping the maximum possible Euclidean distance between the modulated symbols. Furthermore, the proposed DSTS scheme results in a low-complexity MIMO scheme, due to nonemployment of any channel estimation mechanism. Various combinations of source bit coding- (SBC-) aided IJSCD error protection scheme has been used, while considering their identical overall bit rate budget. Artificial redundancy is incorporated in the source-coded stream for the proposed SBC scheme. The motive of adding artificial redundancy is to increase the iterative decoding performance. The performance of diverse SBC schemes is investigated for identical overall code rate. SBC schemes are employed with different combinations of inner recursive systematic convolutional (RSC) codes and outer SBC codes. Furthermore, the convergence behaviour of the employed error protection schemes is investigated using extrinsic information transfer (EXIT) charts. The results of experiments show that our proposed R a t e − 2 / 3 SBC-assisted error protection scheme with high redundancy incorporation and convergence capability gives better performance. The proposed R a t e − 2 / 3 SBC gives about 1.5 dB E b / N 0 gain at the PSNR degradation point of 1 dB as compared to R a t e − 6 / 7 SBC-assisted error protection scheme, while sustaining the overall bit rate budget. Furthermore, it is also concluded that the proposed R a t e − 2 / 3 SBC-assisted scheme results in E b / N 0 gain of 24 dB at the PSNR degradation point of 1 dB with reference to R a t e − 1 SBC benchmarker scheme. Amaad Khalil, Nasru Minallah, Muhammad Asfandyar Awan, Hameed Ullah Khan, Atif Sardar Khan, Atiq ur Rehman 0002 |
Wirel. Commun. Mob. Comput. | 3 |