Address translation is increasingly a performance bottleneck in flash-based SSDs (solid state drives). We propose a hardware-accelerated flash map management unit called FMMU to speed up the address translation. The FMMU operates in a non-blocking manner without any involvement of software and uses in-cache linked list to enhance the performance of flush operations. Simulation study shows that the FMMU improves IOPS (I/O operations per second) by 135 % on average when compared against software-only approaches. The results also show that the performance gap widens as the number of flash chips/buses and the host interface speed increase.

We present a framework called Hierarchically Interacting Logs (HIL) for constructing Flash Translation Layers (FTLs). The main goal of the HIL framework is to heal the Achilles heel —the crash recovery—of FTLs (hence, its name). Nonetheless, the framework itself is general enough to encompass not only block-mapped and page-mapped FTLs but also many of their variants, including hybrid ones, because of its compositional nature. Crash recovery within the HIL framework proceeds in two phases: structural recovery and functional recovery. During the structural recovery, residual effects due to program operations ongoing at the time of the crash are eliminated in an atomic manner using shadow paging. During the functional recovery, operations that would have been performed if there had been no crash are replayed in a redo-only fashion. Both phases operate in an idempotent manner, preventing repeated crashes during recovery from causing any additional problems. We demonstrate the practicality of the proposed HIL framework by implementing a prototype and showing that its performance during normal execution and also during crash recovery is at least as good as those of state-of-the-art SSDs.

NAND flash-based solid state drives (SSDs) are replacing magnetic disks because of their fast random access performance, shock resistance, and low power consumption. However, the number of program and erase cycles that can be performed on NAND flash is limited. To overcome this limitation, SSDs require a sophisticated wear-leveling algorithm which distributes program/erase cycles evenly across all flash blocks. While most of existing wear-leveling algorithms are only based on the erase counts of flash blocks, our empirical study indicates that the erase count alone is not a good wear index which tells us how much a flash block is worn out. This paper proposes a new wear index for MLC NAND flash memory which takes into account more diverse properties of NAND flash memory. To show the effectiveness of the proposed wear index, we also develop a wear-leveling algorithm, named Equalizer. In our evaluation with three realistic workloads, Equalizer based on the proposed wear index improves the effective lifetime of SSDs by up to 145% compared to the existing wear-leveling technique based on the erase count.