Spiking neural networks (SNNs) can improve inference accuracy through joint optimization of synaptic weights and neuronal thresholds. However, mixed-signal neuromorphic processors, which are designed for energy efficiency using analog circuits, face practical limitations. In particular, digital to analog converters (DACs) often lack sufficient resolution to represent the large threshold values required by joint optimization. To address this issue, we propose a mixed-signal neuromorphic processor architecture that shifts threshold control to digital logic. This approach removes the need for high-resolution DACs and allows dynamic threshold adjustment without modifying the analog neural core. We also propose a learning method tailored to this architecture. We evaluate the proposed design on five image classification benchmarks, measuring accuracy, latency, and energy consumption. The results show that our architecture consistently improves accuracy across benchmarks while incurring only minimal latency and energy overhead. This demonstrates that the proven benefits of joint weight and threshold learning can be realized in energy efficient analog hardware.

Neuromorphic Processor eXpress (NPX) is a framework designed to facilitate the development of lightweight neuromorphic processors. To evaluate its efficacy, we conducted a case study involving the FPGA-based implementation of a traffic sign recognition system using an NPX-generated neuromorphic processor. The prototype integrates camera input and OLED output, successfully demonstrating full functionality. This case study confirms that NPX substantially streamlines the design and deployment of efficient neuromorphic processors for embedded artificial intelligence applications.

Neuromorphic inference applications primarily rely on general matrix-matrix multiplication (GEMM) and twodimensional convolution (Conv2D) operations. When conventional artificial neural network (ANN) acceleration techniques are employed, these computations often necessitate extensive data reordering, which imposes significant overheads, especially in lightweight embedded systems with limited CPU and memory bandwidth. To address this challenge, we propose a unified accelerator architecture executing GEMM and Conv2D operations without data reordering. The accelerator is co-designed with a neuromorphic software framework tailored for lightweight embedded systems. To validate effectiveness, we implement a neuromorphic processor incorporating the proposed accelerator on an FPGA. Evaluation results across four representative neuromorphic applications demonstrate that the proposed design reduces execution time and energy consumption by 69% and 89%, respectively, compared to conventional ANN accelerators.

Developing low-power neuromorphic processors capable of inferring outcomes from SNN Frameworks presents significant challenges, largely due to the gap between frameworks and analog circuit-based SNNs. This paper analyzes the root of this gap as stemming from over/underflow issues and proposes mixed-signal neurons as a solution, further developing a neural core composed of these neurons. In the development of the neural core, we incorporate a design methodology for application-specific neural core optimization. We advance to develop a neural engine as an independent IP, ultimately introducing the snnTorch Architecture (STARC), an integrated mixed-signal neuromorphic processor architecture. The STARC processor, developed as a prototype, demonstrates operational correctness and exceptional low-power performance.

Ranging from circuit-level characterization to designing a platform architecture, developing a design automation tool, and fabricating a System on Chip (SoC), this article deals with the entire development process for ultralow-power (ULP) SoCs for Internet-of-Things (IoT) end nodes. More precisely, this article first focuses on the unique characteristics of the ULP circuits, the temperature effect inversion (TEI), i.e., the delay of the ULP circuits decreases with increasing temperature. Existing TEI-aware low-power (TEI-LP) techniques have incredible potential to further reduce the power consumption of conventional ULP SoCs, but there is a critical limitation to be widely adopted in real SoCs. To address this limitation and realize the ULP SoCs that can fully benefit from the TEI-LP techniques, this article proposes a new TEI-inspired SoC platform (TIP) architecture. On top of that, taking into account that the highly complex, time consuming, and labor-intensive development process of these ULP SoCs may hinder their widespread use for IoT end nodes, this article presents a new electronic design automation tool to accelerate ULP SoC development, RISC-V express (RVX). Finally, by using the RVX, this article introduces a TIP prototyping chip fabricated in 28-nm FD-SOI technology. This chip demonstrates that power savings of up to 35% can be achieved by lowering the supply voltage from 0.54 to 0.48 V at 25 °C and 0.44 V at 80 °C while continuing to operate at a target 50-MHz clock frequency.