High performance computing (HPC) systems currently integrate several resources such as multi-cores (CPUs), graphic processing units (GPUs) and reconfigurable logic devices, like field programmable gate arrays (FPGAs). The role of the latter two has traditionally being confined to act as secondary accelerators rather than as main execution units. We perform a deep survey around state of the art research and implementation of HPC algorithms; we extract features relevant to each family and list them as key factors to obtain higher performance. Due to the broad spectra of the survey we only include the most complete references found. We provide a general classification of the 13 HPC families with respect to their needs and suitability for hardware implementation. In addition, we present an analysis based on current and future technology availability as well as in particular aspects identified in the survey. Finally we list general guidelines and opportunities to be accounted for in future heterogeneous designs that employ FPGAs for HPC.

FPGA-based platforms allow implementing reconfigurable systems that can change functionality of portions of hardware at runtime. For this purpose, non-volatile, off-chip storage is required to hold the partial-configuration bitstreams that will be used for reconfiguration. Accessing such devices requires a high CPU usage or a dedicated hardware such as a Direct Memory Access (DMA) module, especially when reading from mass storage units using file systems. Relieving the processor from bitstreams acquisition and reconfiguration control promotes parallelism and better task scheduling. This paper presents a dedicated Intellectual Property (IP) block which efficiently retrieves bitstreams from a FAT16 formatted memory and independently performs partial reconfiguration at the highest possible speed. Three versions of the same module are proposed to enable the creation of systems capable of accessing the memory with different protocols and control units. The evaluation results show the advantages of our approach in terms of reconfiguration and reading speed, reduced area overhead, flexibility and ease of use.