We revisit the specification of control circuits and protocols written as regular expressions, and propose a synthesizable subset of the sequences that can be written in the property specification language and system Verilog assertions standards. We give a formal semantics of the sequence operators that can directly be interpreted in terms of circuits, and provide a modular method to achieve the automatic generation of compliant hardware from specifications written as temporal sequences. The method also generates assertions to check the completeness and consistency of the specifications. Results obtained on classical benchmarks show the efficiency of our technique. Finally, we discuss the applications of our prototype tool in an assertion-based verification flow.

We propose a unifying formalization of the concepts of monitor and reactant, and derive a modular synthesis method to achieve automatic generation of compliant modules from declarative temporal specifications. The founding dependence relation and its hardware interpretation provide an algorithm to automatically decide which signals are observed and which are generated. The method is efficient, and it synthesizes control circuits in a few seconds. The results obtained on classical benchmarks show that our technique compiles properties more efficiently than previous prototype tools.

We propose a linear complexity approach to achieve the automatic synthesis of designs from declarative temporal specifications. From each property, we produce a component that combines the features of signal monitors and generators: the reactant. This paper gives a formalization of a method to automatically decide which signals are observed and which are generated. The method is efficient, and synthesizes control circuits in a few seconds.