A model that utilizes a graph neural network (GNN) is proposed to estimate wirelength in the early stages of physical design. The model predicts the post-routing wirelength of a net, which addresses the limitations of current estimators including half-perimeter wirelength (HPWL) that tend to under-estimate the true post-routed wirelength of complex nets. Utilizing a dataset of 18 benchmark circuits, the GNN achieves an average R2of 0.825, outperforming HPWL, which yields an R2of 0.764. The GNN demonstrates consistent performance across nets of varying lengths, providing significantly improved accuracy over HPWL for long and multi-path nets. The GNN model is differentiable and compatible with gradient-based optimization methods, while providing an 8× improvement in inference time.

With technology scaling, interconnect impedance becomes a dominant factor that affects the performance of integrated circuits. Estimating the interconnect impedance of analog circuits at early design stages has been a persistent challenge, primarily due to the lack of detailed layout information. Even with accurate parasitic extraction after routing, many iterations of modifications to the design are required to compensate for the effects of interconnect impedance. To address this challenge, a novel approach is proposed in this work that leverages graph neural networks (GNNs) for the estimation of the interconnect capacitance of an analog circuit at both the schematic and post-placement stages of the design flow. A device-level circuit is represented as a heterogeneous graph, where two node types are utilized, one representing transistors and the other representing nets. The GNN model, specifically, the relational GraphSAGE network, is applied to update the embeddings of net nodes, which are then used to predict the lumped capacitance of a net. To allow the model to learn the spatial relationships between devices after placement, the pairwise Manhattan distances between devices are utilized as edge weights during the aggregation of node embeddings. A dataset of ten analog circuits is utilized to evaluate the proposed model. The developed GNN model for post-placement prediction of capacitance that utilizes pairwise Manhattan distances results in an R2score of 0.73 and a mean absolute error of 0.26 fF, outperforming both the schematic-level prediction model and the post-placement prediction model that directly utilizes device coordinates as features. Results confirm that the proposed model effectively estimates the interconnect capacitance of analog circuits at early design stages while requiring a small dataset for training.

Recently, graph neural networks (GNNs) have been applied to various circuit applications, where circuit topology is leveraged in the learning of the models. However, the aggregation of GNN models has not accounted for circuit hierarchies. In addition, the generalization of GNNs to distinguish between different circuit topologies is not currently provided, which raises the question of whether one GNN is sufficient to simultaneously model differing circuit graphs. In this work, a graph representation is proposed, based on a given circuit netlist, to model analog circuits at the transistor level. Additional categorical features are included to address the ambiguity in modeling the connections of the terminals of a given transistor. Edge-conditioned convolution (ECC) is utilized, where weight matrices conditioned on the edge attributes are trained in the local neighborhood of a given node. A relational graph is constructed to model groupings of devices for each level of the hierarchy provided by the designer. Each adjacency matrix of the relational graph is processed by a graph isomorphism network (GIN) layer, described as a Circuit-GIN layer, to update the node embeddings. The model consisting of an ECC layer and two Circuit-GIN layers, described as a Circuit-GNN, is trained on data from four op-amp topologies to predict four performance parameters. Results indicate that the ECC-based model outperforms a GCN-based model in the prediction of all of the performance parameters, which results from the additional edge information learned by the ECC layer. With the addition of Circuit-GIN layers, the Circuit-GNN outperforms the ECC-only model by up to 16.7% in$\boldsymbol{R}^{\mathbf{2}}$score. Therefore, aggregation of node embeddings based on device groupings brings additional benefit to guide the GNNs in modeling the performance of analog ICs. The work also validates the expressive power of the proposed GNN model, which generates embeddings that distinguish between different circuit graphs. The generalization of GNNs renders feasible the simultaneous learning from different analog topologies.

A transfer learning technique is proposed that utilizes models trained on data in one technology node to predict the performance of a circuit based on the sizing of transistors in another technology node. Specifically, neural networks optimally trained on data from the source technology node are adopted as pre-trained models. During transfer training, the front layers of the pre-trained models are frozen while the remaining layers are re-trained with significantly less data in the target technology node. The transfer learning technique is applied to the prediction of seven performance metrics of an operational amplifier based on seven design variables that include the sizing of transistors and capacitors. Models trained on a dataset containing 1602 simulated design points from a 180 nm process are transferred to predict the performance metrics of the op-amp utilizing only 100 simulated design points from a 65 nm process. During the training of the transferred models, the learning curve exhibits an improved starting point and a lower asymptotic error. Utilizing the same training set of 100 points from the 65 nm process, applying transfer learning reduces the normalized mean average error (MAE) on the test (inference) set in all cases by up to 50% as compared to training standalone models. For the transferred models, a detailed characterization of the test error as a function of the number of frozen layers is performed. Results indicate that the transferred gain predictor trained with only 100 data points provides a lower test error than the standalone model trained with 1000 data points without transfer learning in a 65 nm process. Therefore, transfer learning improves the sample efficiency of the training of the neural networks used for the prediction of the performance parameters of a circuit, which provides benefit for design migration when the collection of new circuit data is computationally costly in the target process node.