Reconfigurable intelligent surfaces (RIS) can reflect an incoming signal toward a target location to enhance the received signal quality. In most studies, it is assumed that the base station (BS) provides configuration data to an RIS controller. However, for a passive RIS with a high number of elements, this data transmission from the BS can introduce significant delays. This challenge is especially pronounced in vehicular communications, where reflection coefficients must be updated even for a few millimeters of movement. To overcome this limitation, we propose a self-tuning RIS controller that independently calculates the reflection coefficients with minimal input from the BS. Our RIS controller leverages the user’s location information to compute the reflection coefficients in three steps: channel gain calculation, steering vector calculation, and optimal phase control. A pipelined architecture is developed to support these steps in real-time. The proposed VLSI architecture is implemented on an Artix-7 XC7A100TCSG324-1 FPGA to calculate reflection coefficients for a vehicle moving at a 100 kmh speed.

Massive multiple-input multiple-output (MIMO) technology utilizes large antenna arrays at the base-station (BS) to support a large number of users with the same time/frequency resources. Uplink signal detection poses a significant challenge in massive MIMO systems. Although minimum-mean square-error based detectors become the mainstay of classical massive MIMO systems, they require a large-dimensional matrix inversion, which is computationally extensive. This paper proposes a new massive MIMO detector based on the two-parameter over relaxation (TOR) algorithm. The relaxation and acceleration parameters are carefully selected on the basis of the spectral radius to achieve a good balance between the performance and the complexity. Compared to existing linear detectors, the proposed TOR based detector is more stable because of its relaxation and acceleration parameters. The results show that the proposed massive MIMO detector achieves a remarkable performance gain and overall complexity reduction compared to existing detectors, particularly when the number of users is comparable to the number of BS antennas. The proposed TOR detector achieves better performance than the existing detectors when using the same number of iterations.

Open RAN (ORAN, O-RAN) represents a novel industry-level standard for RAN (Radio Access Network), which defines interfaces that support inter-operation between vendors’ equipment and offer network flexibility at a lower cost. Open RAN integrates the benefits and advancements of network softwarization and Artificial Intelligence to enhance the operation of RAN devices and operations. Open RAN offers new possibilities so different stakeholders can develop the RAN solution in this open ecosystem. However, the benefits of Open RAN bring new security and privacy challenges. As Open RAN offers an entirely different RAN configuration than what exists today, it could lead to severe security and privacy issues if mismanaged, and stakeholders are understandably taking a cautious approach towards the security of Open RAN deployment. In particular, this paper analyzes the security and privacy risks and challenges associated with Open RAN architecture. Then, it discusses possible security and privacy solutions to secure Open RAN architecture and presents relevant security standardization efforts relevant to Open RAN security. Finally, we discuss how Open RAN can be used to deploy more advanced security and privacy solutions in 5G and beyond RAN.

Deep learning models usually assume that training dataset and target data have the same distribution. If this is not the case, model mismatch causes performance degradation when the model is used with the real data. With radio frequency (RF) measurements from real data traffic, the exact distribution of the measurements is unknown in many cases and model mismatch is unavoidable. This is known as concept drift, or model mis- specification in deep learning, which we are interested in for cognitive radio dynamic spectrum access predictions. In this paper, we present three concept drift detection methods and their corresponding very large scale integration (VLSI) circuits. The circuits are mapped on a Xilinx Virtex-7 field-programmable gate array (FPGA) and the resource utilization results are provided.

In this article, we propose a novel data detection algorithm and a corresponding VLSI design for massive multiuser (MU) multiple-input-multiple-output (MIMO) wireless systems. Our algorithm uses alternating direction method of multipliers (ADMM)-based infinity-norm-constrained equalization and is called ADMIN. ADMIN is an iterative algorithm that outperforms linear detectors by a large margin when the ratio between the numbers of base-station (BS) and user antennas is small. In the first iteration, ADMIN computes the linear minimum mean-square error (MMSE) solution, which is sufficient when the ratio between the numbers of BS and user antennas is large. We develop time-shared and iterative VLSI architectures for LDL-decomposition-based soft-output ADMIN supporting 16- and 32-user systems. We present application-specific integrated circuit (ASIC) designs for 16-64 antenna base stations in 28-nm CMOS that supports up to 64 quadrature amplitude modulation (QAM). The 16-user ADMIN ASIC achieves 303 Mb/s while dissipating 85 mW. The 32-user ADMIN ASIC achieves 287 and 241 Mb/s while dissipating 121 and 135 mW for 32 and 64 BS antennas, respectively. ADMIN has also been implemented on a Xilinx Virtex-7 field-programmable gate array (FPGA) and is compared with state-of-the-art massive MIMO data detectors.

We propose a novel data detection algorithm and a corresponding VLSI design for large multi-user (MU) multiple-input multiple-output (MIMO) wireless receiver. Our algorithm, referred to as ADMIN, performs alternating direction method of multipliers (ADMM)-based infinity norm constrained equalization. ADMIN is an iterative algorithm that outperforms linear detectors if the number of users is small compared to that of the antennas in base station (BS). ADMIN computes the linear minimum mean-square error (MMSE) solution in the first iteration. It is sufficient when the ratio between the numbers of BS antennas and users is rather large. We develop a time-shared and iterative VLSI architecture for LDL-decomposition based soft-output ADMIN. Our architecture achieves 685.71 Mb/s for linear MMSE and 212.38 Mb/s for ADMIN for a 16-user system that employs 64-QAM in a 28 nm CMOS technology.

Lattice reduction (LR) is a preprocessing technique for multiple-input multiple-output (MIMO) symbol detection to achieve better bit error-rate (BER) performance. In this paper, we propose a customized homogeneous multiprocessor for LR. Each individual core is based on transport triggered architecture (TTA). We propose a few modifications of the popular LR algorithm, Lenstra-Lenstra-Lovász (LLL) for high throughput. High level programming is used to implement the control path of the TTA cores and several special function units are designed to accelerate the program. The multiprocessor takes 187 cycles to reduce a single matrix for LR. The architecture is synthesized on 90 nm technology and takes 405 kgates at 210 MHz.