Sonal Yadav

dblp:138/1096 · DBLP profile ↗
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7ranked-venue papers
5as first author
5since 2021 · last 2025
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 4 first-author · 3 since 2021Computer networks · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author · 1 since 2021
YearPublicationVenuePosition
2025 RL-RD-Net: A latent features integration through representation learning for retinal detachment diagnosis with retinographic color fundus images
Sonal Yadav, R. Murugan, Nishant Sharma, Naveen Kumar Roy, Tripti Goel
Multim. Tools Appl.1
2025 An extensive bibliometric analysis of artificial intelligence techniques from 2013 to 2023
Aditi Bajpai, Sonal Yadav, Naresh Kumar Nagwani
J. Supercomput.2
2024 Trust-based clustering and routing in WSNs using DST-WOA
Shashank Singh 0013, Veena Anand, Sonal Yadav
Peer Peer Netw. Appl.3
2023 Adaptive distribution of control messages for improving bandwidth utilization in multiple NoC
Sonal Yadav, Vijay Laxmi, Hemangee K. Kapoor, Manoj Singh Gaur, Amit Kumar 0046
J. Supercomput.1
2022 Power efficient network selector placement in control plane of multiple networks-on-chip
Sonal Yadav, Ritu Raj
J. Supercomput.1
2020 Multiple-NoC Exploration and Customization for Energy Efficient Traffic Distribution
abstract
Motivation. As more on-chip computation resources are available, the Networks-on-Chip (NoC) power consumption is expected to increase in the future many-core era. Many of these would have to be switched off while inactive to keep power consumption and chip temperature low. However, the NoC infrastructure must be kept alive to serve shared caches and memory accesses. A recent study shows that the proportion of NoC power consumption becomes appreciable in comparison to computation counterpart. A 32 core chip at 45nm substantially raises NoC power ( ~ 42%) among the remaining on-chip active resources (cores, shared caches, memory controllers, PCIe controllers) [1]. Therefore, low power becomes the primary objective for modern NoC designs.
Sonal Yadav, Vijay Laxmi, Manoj Singh Gaur
VLSI-SOC1
2019 Improving Static Power Efficiency via Placement of Network Demultiplexer over Control Plane of Router in Multi-NoCs
abstract
Network Demultiplexer (Net-Demux) is an essential hardware unit in multiple NoCs for traffic distribution between the NoC networks. This paper proposes a novel idea of the placement of Net-Demux at the control plane of switch allocator of the router to improve static power and energy efficiency as compared to conventional data plane placement at the Network Interface (NI).
Sonal Yadav, Vijay Laxmi, Manoj Singh Gaur, Hemangee K. Kapoor
DAC1