Estelle Lauga

dblp:138/2691 · also Estelle Lauga-Larroze · DBLP profile ↗
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8ranked-venue papers
0as first author
5since 2021 · last 2026
0000-0001-6191-789XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 8 · 5 since 2021Software engineering, systems software and programming languages · 1
YearPublicationVenuePosition
2026 Using DC Transistor Characterization Measurements for LNA Design at Cryogenic Temperatures
Giovani Britton, Salvador Mir, Estelle Lauga, Benjamin Dormieu, Jose Lugo, Joao Azevedo, Sebastien Sadlo, Quentin Berlingard, Mikaël Cassé, Philippe Galy
J. Electron. Test.3
2025 Multi-Agent Reinforcement Learning for Performance Calibration and Optimization of Integrated mmW Power Amplifiers
abstract
This paper explores the application of reinforcement learning algorithms to the problem of calibrating and optimizing the performance of an integrated millimeter-wave (mmW) power amplifier (PA). The proposed calibration algorithm is aimed at compensating performance degradation while optimizing power efficiency, by finding the optimum values of a set of on-chip tuning knobs. The developed calibration solution is based on a multiagent deep reinforcement learning algorithm, in which a number of reinforcement learning agents learn to collaborate in order to optimize the complete set of specifications of the circuit under calibration. The proposed technique is validated based on post-layout simulation results of a tunable 60 GHz PA case study implemented in STMicroelectronics 55 nm CMOS technology.
Valentin Coppola, Florent Cilici, Sylvain Bourdel, Estelle Lauga, Salvador Mir, Florence Podevin, Manuel J. Barragan Asian
ATS4
2024 A New Control Law for N-Path Mixer Switches Enhancing Harmonic Rejection
abstract
This paper presents a novel methodology to enhance harmonic rejection in N-Path Mixers thanks to a dedicated switch control law. The proposed method reduces the effective local oscillator distortion, in order to limit unwanted harmonics appearance at the mixer output. This is achieved by using a non-conventional control of the N-path mixer switches, based on level crossing sampling techniques. The methodology strength is its ability to be used with any N-path mixer, whatever the number of paths. The article details how to optimally design the switch control. To validate the effectiveness of the proposed approach, simulations have been conducted on 4-path and 8-path mixers and compared to the corresponding conventional N-path mixers. This analysis shows significant improvements in terms of harmonic rejection thanks to this new methodology.
Hasan Moussa, Estelle Lauga, Laurent Fesquet
VLSI-SoC2
2023 Noise modeling using look-up tables and DC measurements for cryogenic applications
abstract
There is today a lack of mature transistor-level compact models for the simulation of integrated circuits at cryogenic temperatures. This is particularly the case for the simulation of the noise behavior which is critical for most applications. In this paper, we aim at an efficient prediction of the white noise behavior of basic amplifying stages working at RF frequencies and cryogenic temperatures. For this, we propose the use of DC measurements that are incorporated in a Look-Up Table (LUT) and fed to a mathematical noise model. We illustrate the approach for the case of a transistor in common source configuration. The results of circuit simulation of the noise parameters in the standard temperature range are very close to the estimation of the same parameters using the LUT with just DC measurements. The approach can be readily extended to the analysis of circuits with multiple components. Next, the LUT approach is used for estimating the noise parameters at cryogenic conditions, considering DC measurements that have been carried out at these temperatures. The paper illustrates the feasibility of carrying out a cryogenic design using a LUT-based approach while accurate compact models are not yet available.
Giovani Britton, Salvador Mir, Estelle Lauga, Benjamin Dormieu, Quentin Berlingard, Mikaël Cassé, Philippe Galy
VLSI-SoC3
2022 Special Session on RF/5G Test
abstract
This paper presents an innovative integrated load-pull bench at 160 GHz. The proposed system, which is designed in a 55-nm BiCMOS technology, is tailored to deal with all of the measurement functions including signal generation, shaping, and magnitude and phase measurement. This system will allow precise characterization of Devices-Under-Test (DUTs) (i.e., circuits and/or devices) when integrated together with the DUT. In addition, the proposed system could also be envisioned as a System-on-Chip (SoC) that, when reported into an RF probe, could serve as a test bench for any integrated circuit.
William R. Eisenstadt, Mark Roos, Devin Morris, Jose-Luis Gonzalez Jimenez, Christopery Mounet, Manuel J. Barragan Asian, Gildas Léger, Florent Cilici, Estelle Lauga, Salvador Mir, Sylvain Bourdel, Marc Margalef-Rovira, Issa Alaji, Haitham Ghanem, Guillaume Ducournau, Christophe Gaquière
ETS9
2019 On the use of causal feature selection in the context of machine-learning indirect test
abstract
The test of analog, mixed-signal and RF (AMS-RF) circuits is still considered as a matter of human creativity, and although many attempts have been made towards their automation, no accepted and complete solution is yet available. Indeed, capturing the design knowledge of an experienced analog designer is one of the key challenges faced by the Electronic Design Automation (EDA) community. In this paper we explore the use of causal inference tools in the context of AMS-RF design and test with the goal of defining a methodology for uncovering the root causes of performance variation in these systems. We believe that such an analysis can be a promising first step for future EDA algorithms for AMS-RF systems.
Manuel J. Barragan Asian, Gildas Léger, Florent Cilici, Estelle Lauga, Sylvain Bourdel, Salvador Mir
DATE4
2019 Yield Recovery of mm-Wave Power Amplifiers using Variable Decoupling Cells and One-Shot Statistical Calibration
abstract
Integrated millimeter-wave (mm-wave) circuits fabricated in current nanometric processes are especially sensitive to process variations. This issue produces shifts in the circuit performance that may significantly reduce the fabrication yield. In this line, per-die characterization and trimming are usually required for mm-wave integrated circuits, but this is an expensive and time-consuming task to be performed at the production line. Embedded calibration for mm-wave circuits is an appealing alternative to enhance yield that may overcome some of these issues. In this work we present a two-stage 60 GHz power amplifier (PA), designed in STMicroelectronics 55 nm CMOS technology, that features a one-shot calibration procedure for process variation compensation based on non-intrusive process monitors. We present the design of a tuning knob based on variable decoupling cells which have been implemented within the PA for calibration purposes. The proposed one-shot calibration procedure reads the output of the embedded process monitors and then relies on a machine learning regression model to find the best configuration of the tuning knobs for optimizing the performance of the circuit and enhance fabrication yield.
Florent Cilici, Manuel J. Barragan Asian, Salvador Mir, Estelle Lauga, Sylvain Bourdel, Gildas Léger
ISCAS4
2018 Assisted test design for non-intrusive machine learning indirect test of millimeter-wave circuits
abstract
The functional test of millimeter-wave (mm-wave) circuitry in the production line is a challenging task that requires costly dedicated test equipment and long test times. Machine learning indirect test offers an appealing alternative to standard mm-wave functional test by replacing the direct measurement of the circuit performances by a set of indirect measurements, usually called signatures. Machine learning regression algorithms are then used to map signatures and performances. In this work, we present a generic and automated methodology for finding an appropriate set of indirect measurements and assisting the designer with the necessary Design-for-Test circuit modifications. In order to avoid complex design modifications of mm-wave circuitry, the proposed strategy is targeted at generating a set of non-intrusive indirect measurements using process variation sensors not connected to the Device Under Test (DUT). The proposed methodology is demonstrated on a 60 GHz Power Amplifier designed in STMicroelectronics 55 nm BiCMOS technology.
Florent Cilici, Manuel J. Barragan Asian, Salvador Mir, Estelle Lauga, Sylvain Bourdel
ETS4