This thesis presents an innovative Physically Unclonable Function (PUF) implemented in 600 nm Indium-Gallium-Zinc-Oxide (IGZO) Thin-Film Transistor (TFT) technology, fabri- cated on Flexible Integrated Circuits (FlexICs). The proposed architecture takes advantage of device level randomness to produce distinct and repeatable digital responses by utilizing the intrinsic Threshold Voltage (Vth) variability of IGZO TFTs as a physical entropy source. Oxide TFTs, as opposed to conventional Complementary Metal-Oxide-Semiconductor (CMOS)-based implementations, enable compatibility with low temperature, large area and mechanically flexible substrates. This approach is particularly well suited for the next generation of Internet of Things (IoT) and wearable electronic systems. The circuit architecture is based on a differential current comparison mechanism, where two transistor arrays are sequentially evaluated and their discharge characteristics are compared to produce a digital output. Cadence Virtuoso transient simulations were statistically modeled using the experimentally extracted Vth distributions from manu- factured IGZO TFT matrices. This allowed for precise analysis of entropy quality and robustness. Nine National Institute of Standards and Technology (NIST) SP 800-22 statis- tical test suites were successfully passed by the resultant bitstreams, demonstrating high entropy and consistent randomness across several simulated instances. Additionally, transient noise simulations were performed to assess stability under process and environmental fluctuations. The bitstream demonstrated a Bit Error Ratio (BER) below 0.4% at the optimal comparator threshold. Overall, the proposed IGZO-TFT PUF demonstrates that thin-film oxide electronics can serve as a foundation for intrinsic, low cost and hardware-based security primitives, suitable for secure identification in flexible and large area electronic systems.

As the demand for secure Internet of Things (IoT) devices increases, the need for hardware security solutions has become more critical, particularly in applications with strict power and area constraints. Thin-film transistors (TFTs) are an emerging technology, that enables the integration of complex circuits onto thin, flexible substrates offering both low-cost manufacturing and compatibility with large-area system implementations. This paper, presents, to the best of the authors’ knowledge, the first true random number generator (TRNG) based on jittered oscillator sampling, implemented in 600 nm Indium-Gallium-Zinc-Oxide (IGZO) TFT flexible integrated circuits (FlexICs) technology.The proposed TRNG achieves a throughput of 1.33 Mbits/s, an energy consumption of 4.68 nJ/bit, and occupies an area of 0.920 mm2. The TRNG showed promising results by passing 8 NIST (National Institute of Standards and Technology) randomness tests under nominal conditions. This opens new opportunities for embedding security primitives in flexible electronics, allowing for integration of hardware security in wearable electronics, biomedical devices, communication tags and other applications.

This paper proposes a simple thermal noise cancellation technique to effectively reduce the output noise in predictive integrators. By combining a low-gain two-stage amplifier and a small auxiliary noise-cancelling capacitor, the output noise is highly attenuated. Simulation results for a classic Nagaraj-Ki predictive integrator, considering real MOS switches, demonstrate that the output thermal noise can be reduced up to 87%.

This paper presents a capacitance readout circuit with high sensitivity and low power consumption using amorphous-Indium-Gallium-Zinc-Oxide thin-film transistors (a- InGaZnO TFTs). A relaxation oscillator is proposed to convert the sensor output (capacitance) into frequency. The proposed circuit has bootstrapping load to improve the output voltage swing using unipolar transistors. A differential to single ended converter and a buffer are used to get rail to rail output voltage. Simulation results show an improvement in sensitivity (832 Hz/pF) and power consumption (1.4 mW) as compared to the conventional ring oscillator based designs (142 Hz/pF, 1.9 mW) when circuits are simulated with a power supply of 10V, without compromising voltage swing. Therefore, this circuit finds potential application to implement sensing systems with flexible electronics.

This paper presents a novel mostly passive Δ-Σ ADC using amorphous Indium Gallium Zinc Oxide (a-IGZO) thin-film transistors (TFTs). The ADC circuit consists of passive elements (resistors and capacitors), a novel dynamic comparator, a D-Flip Flop and a pseudo-CMOS BS inverter. In-house oxide TFT model is used for circuit simulations in Cadence environment. The proposed ADC results in effective-number-of-bits (ENOB) of 11.2 bits and a figure-of-merit (FOM) of 0.15 μJ/conversion step at 2 kHz sampling frequency with a 10 V power supply. This circuit would find potential applications in biomedical wearable systems, in which, the ADC is probably the most important block.

This paper presents a novel high speed operational amplifier using a-IGZO TFTs for a given technology, without changing device structure, processing conditions and materials. In the proposed design, a negative capacitance generator (NCG) is employed, using a-IGZO TFTs, which is connected to the output of a positive feedback operational amplifier. This technique helps to move the output pole of the amplifier to very high frequency by reducing the overall equivalent capacitance (Ceq) at the output node, as the negative capacitance is in parallel with Ceq. By using this technique, the unity gain bandwidth (GB) of the opamp is increased from 486 kHz to 1.474 MHz without compromising other performance metrics, such as, gain and stability (phase margin). However power consumption is increased from 0.3mW to 0.6 mW, when the simulations took place with in-house IGZO TFT models. Both NCG and the amplifier were designed with a minimum feature size of 10 μm and a power supply of 10V and 15V, respectively.

This paper presents a low-power ethanol sensing read-out circuit using amorphous-Indium-Gallium-Zinc-Oxide thin-film transistors (a-InGaZnO TFTs). The read-out circuit is implemented with a proposed low-power high-speed ring oscillator (RO). The proposed RO employs bootstrapped pseudo-CMOS inverter, whose delay and power are reduced by using intermediate signals generated within the RO, hence, ensuring a high frequency of oscillations and low-power consumption. This design further ensures improved sensitivity of the readout circuit. To validate the proposed idea, 9-stage conventional low-power and proposed ROs have been designed and simulated using in-house a-InGaZnO TFT models at a supply voltage of 8V. Simulation results show that the proposed RO provides 11.8% improvement in the frequency of oscillations and 18.5% reduction in power consumption compared to the conventional design. Further, the proposed circuit has shown an improvement of 9% in the sensitivity compared to the conventional design. Therefore, this circuit finds potential application in read-out sensing systems.

This paper reports a novel bootstrapping circuit with IGZO TFTs to generate on-chip power supply, mainly for real-time flexible wearable continuous health monitoring system. In order to ensure a compact and reliable system without complex external connections, on-chip power supply is required, to drive biological signal processing or conditioning circuits with IGZO TFTs. Though, integrated system (circuits with oxide TFTs and thin film batteries) can be achieved with printing technique, with the state of art, commercially available thin film printed batteries are confined to 3 V. Typically, flexible electronics with IGZO TFTs needs a power supply > 5 V (depending on the dielectric). The proposed bootstrapping (BS) circuit with IGZO TFTs can generate 2*VDDand 3*VDDwith the printed batteries output voltage of around 3 V. The proposed circuit is tested with an input voltage spanning between 2 to 10 V and clock frequency up to 1 MHz. When the input voltage is 3 V with the load of 5 MΩ and 2 MΩ, the output which is acquired is 7.9 V and 6.4 V, respectively, with the respective power dissipation of 24.9 μW and 50.8 μW. The circuit simulations are carried out using IGZO TFT model in cadence virtuoso environment, which demonstrate that the BS circuit plays a vital role in the on-chip supply generation for wearable biomedical systems.

This paper presents a voltage controlled oscillator (VCO) using amorphous Indium Gallium Zinc Oxide (a-IGZO) thin-film transistors (TFTs). This circuit consists of a high-gain OpAmp, a comparator and a relaxation oscillator. The implemented relaxation oscillator shows a power consumption of 700 μW, when it is simulated with a supply rail of ±5 V. It shows a frequency of oscillation range from 327 to 560 Hz, when the tuning capacitance value varies from 1.6 to 5 pF. On the other hand, the VCO has a power dissipation of 1.3 mW with frequency ranging from 400 to 556 Hz with a controlling voltage from −5 to 5 V. In-house oxide TFT model is used for circuit simulations in Cadence environment. This circuit finds potential applications in large-area flexible systems, namely smart packaging, biomedical and wearable systems, which needs clocks with different frequencies.

A novel linear analog adder is proposed only with n-type enhancement IGZO TFTs that computes summation of four voltage signals. However, this design can be easily extended to perform summation of higher number of signals, just by adding a single TFT for each additional signal in the input block. The circuit needs few number of transistors, only a single power supply irrespective of the number of voltage signals to be added, and offers good accuracy over a reasonable range of input values. The circuit was fabricated on glass substrate with the annealing temperature not exceeding 200° C. The circuit performance is characterized from measurements under normal ambient at room temperature, with a power supply voltage of 12 V and a load of ≈ 4 pF. The designed circuit has shown a linearity error of 2.3% (until input signal peak to peak value is 2 V), a power consumption of 78 μW and a bandwidth of ≈ 115 kHz, under the worst case condition (when it is adding four signals with the same frequency). In this test setup, it has been noticed that the second harmonic is 32 dB below the fundamental frequency component. This circuit could offer an economic alternative to the conventional approaches, being an important contribution to increase the functionality of large area flexible electronics.

This paper presents a low-offset comparator based on n-type amorphous indium gallium zinc oxide thin-film transistors (TFTs). An a-Si:H TFT model was adapted to fit the electrical characterization data obtained for these devices. The proposed comparator comprises three pre-amplification stages, a positive-feedback analog latch and a fully dynamic digital latch. Simulation results show that the proposed circuit can work at several tens of kHz, with an accuracy of the order of 10 mV, considering a supply voltage of 10 V and a current consumption of 380 μA. Monte-Carlo simulations exhibit a 1-sigma random offset voltage smaller than 10 mV and 40 mV, respectively, with and without using autozeroing techniques.