Generative adversarial networks (GANs) have been widely applied in the field of meteorological research, particularly in the downscaling of images due to their ability to generate super-resolution images. In recent years, numerous researchers have combined GANs with recurrent neural networks (RNNs) to address the issue of meteorological super-resolution. However, these models do not take into account the spatial variations of meteorological sequences. In this paper, we propose a super-resolution method named RN-STLSTM-GAN, which combines GANs with RN-STLSTM and ESA networks to learn the spatiotemporal features of meteorological sequences. Specifically, we first apply the RN-STLSTM at the initialization of the generator and discriminator to learn the spatiotemporal relationships between sequential images. Second, an ESA network is combined with the RN-STLSTM structure to enhance the learning of spatial features. Thirdly, LeakyReLU is used as the activation function for both the generator and discriminator to minimize the loss of image data during model training. Experiments conducted on the NJU-CPOL datasets demonstrate that our proposed method outperforms other existing methods and can generate realistic and temporally consistent super-resolution sequences for datasets at different heights.

The FPGA circuit design usually adopts full-custom design method, it indicates that it is difficult to design and optimize an FPGA manually. So, we present FPTLOPT (FPGA Transistor-Level Optimization Tool) which supports a more complex FPGA architecture called general routing matrix (GRM) architecture, and also has higher-accuracy and higher-speed than COFFE [1]. To fit a more complex FPGA architecture, we use the regular matching method to automatically extract the circuits type and build the circuits netlist; To get the higher-accuracy, we predict the layout area by area model we build, then we precisely predict the layout post simulation delay by load model we build; To get the higher-speed, we devise the variable range greedy algorithm, to expanding range automatically. We also provide equalization kernel multi-thread acceleration that can change the thread number according to the current CPU hardware environment. The experimental results illustrate that FPTLOPT supports the optimization of GRM architecture and build the key sub-circuit netlist. Also, the area prediction is by maximum of 43%, the delay get from delay prediction is 28% more precise than the ones in COFFE. Besides, quickly gets the optimal transistor sizing results for different optimization objectives. For the same circuit, the optimization speed is 19.96 times faster than COFFE.

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Due to its dominance in the whole chip area, power and delay, the FPGA interconnect circuits are traditionally designed by full custom design method. We present an automated transistor-level sizing optimization methodology for GRM FPGA interconnect circuits. In order to get accurate and effective predicated area, the commonly used diffusion sharing, transistor folding and inputs sharing are considered. To get the accurate and effective delay value, we avoid the inaccuracy of using linear device model, and use two schemes to build wire model: the wire within a circuit and the wire between interconnect circuits. To decrease simulation time, we propose multi-thread acceleration method and the Minimum-Final-Delay (MFD) algorithm which optimizes interconnect circuit as a whole, not separated part. For switch box optimization, MFD algorithm requires 38% less number of simulations than COFFE's algorithm. We use 65nm CMOS process technology for evaluation. For different optimization strategy, we emphasize either representative critical path delay or overall layout area. Compare to full-custom design method, the global cost can be decrease by 3% ~ 17%. For different transistor sizing combinations, 10/50 threads can be ~ 9X/15X faster than single-thread. Compared with the manual design method, our optimization methodology explores larger design space, and it decreases the circuit design optimization time from months to hours.

As the capacity of FPGA increases, FPGA placers that adopt Simulated Annealing (SA) algorithm take more and more runtime. To solve this problem, this paper presents HCAS, a Hybrid algorithm Combining Analytical method and SA. There are three modifications in HCAS: (1) In global placement, faster and better result is realized by modified analytical algorithm. (2) In detailed placement, proper tradeoff is made between quality and runtime through improvement of SA. (3) Optimization workload of timing and wirelength is reasonably assigned between global and detailed placement according to algorithm features. HCAS is implemented in the newest VPR. Compared to VPR placer, it obtains a speedup of 11.1x, with 3% shorter wirelength and 5% smaller critical path delay. Compared to other analytical-based hybrid placers, HCAS achieves greater speedup and enhancement of placement quality is similar or better.

Due to its dominance in FPGA area and delay, the interconnect circuit is traditionally designed and optimized in full customized fashion, which can be extremely time consuming. In this paper, we propose an automated transistor-level sizing optimization method for the widely-used General Routing Matrix FPGA interconnect circuits with the following three features: (1) an area model that takes into account the commonly used diffusion sharing, transistor folding and inputs sharing techniques in order to have an accurate area predication; (2) an accurate and effective non-linear delay model that treats the wire within a circuit and the wire between interconnect circuits separately; (3) a multi-thread acceleration method and the Minimum-Final-Delay algorithm to speed-up the simulation. The global optimization cost is measured by the product of the interconnect circuit area and the representative path delay based on our proposed models. The cost reduces 10.9%, when we use 65nm CMOS process chip for evaluation. The simulation time for different transistor sizing combinations is improved by 9X and 15X when 10 and 50 threads are used, respectively, faster than single-thread. Compared with the manual design method, our proposed optimization approach explores a larger design space and reduces the optimization time from months to hours.