Demo Data from EDBT 2026 / reviewers in the wild / expert
Shyamapada Mukherjee
dblp:139/0493
· DBLP profile ↗
3ranked-venue papers
2as first author
2since 2021 · last 2026
0000-0003-0062-9709ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author · 1 since 2021Databases, data management, data science and information retrieval · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% | |
| Theoretical computer science
1 paper |
Automated reasoning and model checking · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design › routing
FPGA routing |
0.2 | 1 | 2016 | Nearly-2-SAT Solutions for Segmented-Channel Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016 |
Electronic design automation
physical design |
0.2 | 1 | 2016 | Nearly-2-SAT Solutions for Segmented-Channel Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016 |
Electronic design automation › physical design
routing |
0.2 | 1 | 2016 | Nearly-2-SAT Solutions for Segmented-Channel Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016 |
Electronic design automation › physical design › routing › VLSI routing
SAT-based routing |
0.2 | 1 | 2016 | Nearly-2-SAT Solutions for Segmented-Channel Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016 |
Electronic design automation › physical design › routing › FPGA routing
segmented channel routing |
0.2 | 1 | 2016 | Nearly-2-SAT Solutions for Segmented-Channel Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016 |
Automated reasoning and model checking
satisfiability |
0.1 | 1 | 2016 | Nearly-2-SAT Solutions for Segmented-Channel Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016 |
Methods — techniques the papers use, named apart from their topics
nearly-2-SAT · 0.5Boolean CNF formulation · 0.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | A unified graph neural network pipeline for hardware Trojan detection
Shyamapada Mukherjee, Ananya Jyoti Mahanta |
Integr. | 1 |
| 2023 | An extract-then-abstract based method to generate disaster-news headlines using a DNN extractor followed by a transformer abstractor
Sumanta Banerjee, Shyamapada Mukherjee, Sivaji Bandyopadhyay, Partha Pakray |
Inf. Process. Manag. | 2 |
| 2016 | Nearly-2-SAT Solutions for Segmented-Channel RoutingabstractThis paper proposes a nearly-2-satisfiability (SAT) routing solution for segmented-channels in row-based field programmable gate array architectures. Both dogleg-free routing and routing with dog-legging are considered here. The constraints for these problems have been expressed as Boolean conjunctive norm form (CNF) clauses and the conjunction of these clauses creates a Boolean function. The formulation ensures that the maximum number of clauses created consist of 2 literals. Hence, it converts the routing problem, which is an optimization problem, to a nearly-2-SAT problem. Since 2-SAT, i.e., checking the SAT of a Boolean CNF function with clauses having maximum 2 literals, is polynomial time computable, a nearly-2-SAT problem will also compute faster than other SAT-based solutions. We have used statistical distributions to experimentally test the efficiency of our technique and compared the performance with existing SAT-based technique for segmented-channel routing. The results show that more than 90% clauses are 2-literal for both routing options in the proposed methodology and around 20× speedup is observed with respect to existing technique. Shyamapada Mukherjee, Suchismita Roy |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |