This paper provides a case study for enhancing Threshold Logic (TL) performance by exploiting the back-gate bias control offered by 22nm Fully Depleted Silicon-on-Insulator (FDSOI) technology across three process corners and five temperatures under transient noise. The paper demonstrates how back-gate biasing changes the threshold voltage and reduces the offset from 500µV to 400µV. Moreover, the improvement of 200µV in symmetric offset range and 100µV in input resolution are observed in comparison to conventional biasing. These improvements come at the cost of increased energy dissipation at temperatures higher than 27°C. The accuracy detection is slightly better under conventional biasing with an improvement of 30µV differential input range at 125°C. The back gate biasing results in a marginal shift of the graph by 0.03% at −55°C to a maximum of 8% at 125°C in comparison to the conventional biasing.

This paper compares the cross-technology performance of an improved Adiabatic Capacitive Neuron (ACN) design variant. Performance is compared across three commercially available CMOS technologies: two bulk 180nm and 130nm and a 22nm, ultra-low-power Fully-Depleted Silicon-On-Insulator (FDSOI) technology for extreme-edge neuromorphic computing. For comparison, we implement an ACN that is functionally equivalent to a software-trained Artificial Neuron (AN) with binary inputs and outputs, as well as positive, real-valued weights. The paper also demonstrates how back-gate biasing in FDSOI can be used to manipulate the threshold voltage and thus reduce threshold and leakage losses, further enhancing the energy performance of the adiabatic components of the ACN. Simulation results demonstrate that the 22nm technology node dramatically outperforms its 180nm and 130nm counterparts in energy savings, especially at frequencies of 10MHz and above. At 100MHz the synapse energy savings are 4.8x and 3.5x, while the threshold logic savings are 10x and 4.5x when compared to 180nm and 130nm technologies respectively.