Commercial-off-the-shelf (COTS) platforms feature several cores that share and contend for memory resources. In real-time system applications, it is of paramount importance to correctly estimate tight upper bounds to the delays due to memory contention. However, without proper support from the hardware (e.g. a real-time bus scheduler), it is difficult to estimate such upper bounds.This work aims at avoiding contention for a set of tasks modeled using the Predictable Execution Model (PREM), i.e. each task execution is divided into a memory phase and a computation phase, on a hardware multicore architecture where each core has its private scratchpad memory and all cores share the main memory. We consider non-preemptive scheduling for memory phases, whereas computation phases are scheduled using partitioned preemptive EDF. In this work, we propose three novel approaches to avoid contention in memory phases: (i) a task-level time-triggered approach, (ii) job-level time-triggered approach, and (iii) on-line scheduling approach. We compare the proposed approaches against the state of the art using a set of synthetic experiments in terms of schedulability and analysis time. Furthermore, we implemented the different approaches on an Infineon AURIX TC397 multicore microcontroller and validated the proposed approaches using a set of tasks extracted from well-known benchmarks from the literature.

Summary Neuromorphic architectures are one of the most promising architectures to reduce the energy consumption of tomorrow's computers. These architectures are inspired by the behavior of the brain at a fairly precise level and consist of artificial spiking neural networks. To optimize the implementation of these architectures, we propose in this article a novel progressive network compression and reinforcement technique. This technique consists of two functions: progressive pruning and dynamic synaptic weight reinforcement, which we apply after each training batch. The proposed approach delivers a highly compressed network (up to 80% of compression rate) while preserving the network performance when tested with MNIST.

Bio-inspired computing architectures enable ultra-low power consumption and massive parallelism using neuromorphic computing, which is apt to implement Spiking Neural Networks (SNN). Such architectures are particularly suitable for energy-constrained applications. A deeper understanding of Spiking Neural Networks (SNN) behavior during training is needed to improve these architectures. This paper presents VS2N, a web-based tool for interactive visualization and analysis of SNN activity over time. This simulator-independent tool offers a way to examine, analyze and validate different hypotheses about SNN activity. We present available analysis modules and use-cases of the tool as an example.

Summary Three‐dimensional Network‐on‐Chip (3D NoC) is a promising solution for solving 2D NoC problems while optimizing the system's performance. Mapping applications in 3D NoC is a crucial step as it has a significant impact on overall system performance. Moreover, multi‐task supported processing elements (PEs) are needed to run multiple applications and provide more scalability. Most of the existing 3D mapping approaches consider only the single‐task platform. In this paper, we propose an efficient multi‐task mapping algorithm targeting regular 3D NoC that allows an incremental mapping and parallel execution of many applications onto different partitions on the 3D NoC. The proposed mapping algorithm is composed of three main steps aiming to reduce the communications overhead, exploiting the benefits of vertical links and improving the performances. The algorithm has been evaluated with various random and realistic benchmarks and compared with existing mapping algorithms for 3D NoC. The experimental results demonstrate that the proposed mapping strategy achieves significant performance in terms of communication cost, energy consumption and execution time.