Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data.

Daifeng Guo

dblp:139/2461 · DBLP profile ↗
← Back
5ranked-venue papers
3as first author
0since 2021 · last 2020
0000-0003-4935-6609ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%
Theoretical computer science
1 paper
Graph algorithms and graph theory · 100%

Topics — the 9 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design
0.722020
On Coloring Rectangular and Diagonal Grid Graphs for Multipatterning and DSA Lithography · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Layout optimization and template pattern verification for directed self-assembly (DSA) · DAC 2015
Electronic design automation › physical design › lithography
directed self-assembly
0.412020
On Coloring Rectangular and Diagonal Grid Graphs for Multipatterning and DSA Lithography · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation › physical design
lithography
0.412020
On Coloring Rectangular and Diagonal Grid Graphs for Multipatterning and DSA Lithography · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation › physical design › lithography
multiple patterning lithography
0.412020
On Coloring Rectangular and Diagonal Grid Graphs for Multipatterning and DSA Lithography · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Graph algorithms and graph theory
graph algorithms
0.412020
On Coloring Rectangular and Diagonal Grid Graphs for Multipatterning and DSA Lithography · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Graph algorithms and graph theory
graph coloring
0.412020
On Coloring Rectangular and Diagonal Grid Graphs for Multipatterning and DSA Lithography · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation
hardware verification and test
0.212015
Layout optimization and template pattern verification for directed self-assembly (DSA) · DAC 2015
Electronic design automation › physical design
layout optimization
0.212015
Layout optimization and template pattern verification for directed self-assembly (DSA) · DAC 2015
Electronic design automation › physical design
layout verification
0.212015
Layout optimization and template pattern verification for directed self-assembly (DSA) · DAC 2015

Methods — techniques the papers use, named apart from their topics

k-coloring analysis · 0.9NP-completeness proof · 0.9directed self-assembly · 0.2block copolymer lithography · 0.2
YearPublicationVenuePosition
2020 On Coloring Rectangular and Diagonal Grid Graphs for Multipatterning and DSA Lithography
abstract
Rectangular grid graph (RGG) and diagonal grid graph (DGG) are induced subgraphs of a rectangular or diagonal grid, respectively. Their k-coloring problem has direct applications in printing contact/via layouts by multipatterning lithography (MPL). However, the problem in general is computationally difficult for k 2, while it remains an open question on grid graphs due to their regularity and sparsity. On the other hand, directed self-assembly (DSA) technique can work with MPL to optimize the graph by grouping neighboring vertices such that k can be reduced, but the problem of deploying the grouping for coloring is even more intractable. In this paper, we study both of the k-coloring problems, with and without DSA grouping, on RGG and DGG. Without grouping, a complete k-coloring analysis is conducted and particularly the NP-completeness of 3-coloring on a diagonal grid is proved. When considering grouping, we present a 3-coloring solution and prove the NP-completeness to solve the problem of k = 2.
Daifeng Guo, Hongbo Zhang 0001, Martin D. F. Wong
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2018 On coloring rectangular and diagonal grid graphs for multiple patterning lithography
abstract
Rectangular and diagonal grid graphs are induced subgraphs of a rectangular or diagonal grid respectively. Their k-coloring problem has direct applications in printing contact/via layouts by multi-patterning lithography (MPL). However, the problem in general is computationally difficult for k>2, while it remains an open question on grid graphs due to their regularity and sparsity. In this paper, we conduct a complete analysis of the k-coloring problems on rectangular and diagonal grid graphs, and particularly the NP-completeness of 3-coloring on a diagonal grid graph is proved. In practice, we propose an exact 3-coloring algorithm. Experiments are conducted to verify its effectiveness and performance. Extensions and other results are also discussed.
Daifeng Guo, Hongbo Zhang 0001, Martin D. F. Wong
ASP-DAC1
2015 Polynomial time optimal algorithm for stencil row planning in e-beam lithography
abstract
Electron beam lithography (EBL) is a very promising candidate for integrated circuit (IC) fabrication beyond the 10 nm technology node. To address its throughput issue, the Character Projection (CP) technique has been proposed, and its stencil planning can be optimized with aware of overlapping characters. However, the top level 2D stencil planning problem has been proved to be an NP-hard problem. As its most essential step, the 1D row ordering is believed hard as well, and no polynomial time optimal solution has been provided so far. In this paper, we propose a polynomial time optimal algorithm to solve the row ordering problem, which serves as the major subroutine for the entire stencil planning problem. Proof and experimental results are also provided to verify the correctness and efficiency of our algorithm.
Daifeng Guo, Yuelin Du, Martin D. F. Wong
ASP-DAC1
2015 Layout optimization and template pattern verification for directed self-assembly (DSA)
abstract
Recently, block copolymer directed self-assembly (DSA) has demonstrated great advantages in patterning contacts/vias for the 7 nm technology node and beyond. The high throughput and low process cost of DSA makes it the most promising candidate in patterning tight pitched dense patterns for the next generation lithography. Since DSA is very sensitive to the shapes and distributions of the guiding templates, it is necessary to develop new EDA algorithms and tools to address the patterning rules and constraints of the process. This paper presents a set of DSA-aware optimization techniques targeting the most urgent problems for DSA technology, including layout optimization and template pattern verification.
Zigang Xiao, Daifeng Guo, Martin D. F. Wong, He Yi, Maryann C. Tung, H.-S. Philip Wong
DAC2
2013 Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library
abstract
At the 10 nm technology node, the contact layers of integrated circuits (IC) designs are too dense to be printed by single exposure using 193 nm immersion (193i) lithography. Among all the emerging patterning approaches, block copolymer directed self-assembly (DSA) is a promising candidate with high throughput and low cost for sub-20 nm features. Traditionally, the study of DSA has focused on achieving periodic regular patterns over large area. Realizing that long range order is not needed for patterning irregularly distributed contact holes, we use topographical guiding templates to alter the natural symmetry of block copolymer and achieve controlled irregular DSA patterns. However, DSA patterning must satisfy the overlay accuracy requirements while the guiding templates also need to be printable by conventional lithography. This presents a unique opportunity of DSA patterning and layout design co-optimization for improving the manufacturability of DSA. This paper discusses the DSA-aware contact layer optimization problem for 10 nm 1D standard cell library. For the first time we propose a cost function for each DSA template based on its overlay accuracy performance. Then given a standard cell library, we simultaneously optimize the layouts of every cell, such that the contact layer of any cell in the library can be fully patterned by a set of guiding templates, and the total cost of the templates is minimal. This optimization problem is first proved to be NP-hard and formulated as a Weighted Partial Maximum Satisfiability (MAXSAT) problem, which can be optimally solved with a public SAT solver. Then we propose a bounded approximation algorithm that solves the problem much more efficiently. The experimental results demonstrate that our approach is remarkably promising in practice and validate the proposed optimization problem.
Yuelin Du, Daifeng Guo, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang 0001, Qiang Ma 0002
ICCAD2