We introduce a generalized, efficient, and accurate power abstraction model and generation techniques for complex IP blocks. This is based on the contributor based power modeling concept, which exploits the nature of power consuming components in a design being inherently separable. The generated power abstraction is Process, Voltage and Temperature (PVT) independent, thus enabling very efficient hierarchical power analysis. Our approach constitutes the industry's first design methodology to automatically generate PVT independent contributor based abstracts. We also describe extensions to the power contributor concept to model dynamic power. Extensive analysis and results on real industry designs to study the accuracy impacts of abstraction as a function of design types and sizes are presented. We also present model to hardware correlation experiments demonstrating the application of this abstraction based methodology on the IBM Power7+ server microprocessor chip.

IBM's high-performance microprocessor designs leverage internally developed electronic design automation tools to create high-frequency, power efficient, and robust microprocessors. This paper describes some of the tools employed in the custom circuit design methodology in IBM. The tools described include a transistor-level block-based static timer, a static noise analysis methodology, and a transistor width tuner that optimizes performance and area. We also describe the application of electrical rule checking used to enforce consistent design practices. Finally, we discuss a macro extraction tool that determines parasitic resistance and capacitance of interconnect from a layout.