Fusarium Head Blight (FHB) poses a substantial threat to global wheat production and food security. Current manual detection methods are inadequate due to their labor-intensive nature and inaccuracies, whereas advancements in Unmanned Aerial Vehicle (UAV) and object detection technologies have improved detection accuracy but still struggle with accurately defining disease boundaries. This study presents MFWNet, a robust UAV-based semantic segmentation model specifically designed for FHB detection. MFWNet innovatively integrates Multi-scale Feature Fusion and Wavelet Convolution, optimizing large kernel convolutions. Key innovations include the Efficient Contextual Convolutional Module (ECCM) for multi-scale feature extraction and fusion and the Feature Enhancement (FE) Module for improved feature representation focused on FHB, thereby improving contextual understanding and boundary precision. Additionally, the implementation of semi-supervised learning for image annotation significantly reduces the need for extensive labeled datasets, which decreases manual annotation efforts and boosts scalability. A wheat FHB dataset consisting of 1,807 pixel-level annotated images was constructed for this purpose. Remarkably, with only 10.15 million parameters, MFWNet achieves a mean Accuracy of 85.78% and a mean Intersection over Union of 73.54%, outperforming nine comparative models in terms of accuracy and efficiency. This method offers an effective solution for large-scale UAV-based FHB detection under real-field conditions, with significant implications for food security.

Over the last few years, hybrid solid-state drives (SSDs) have been widely adopted due to their high performance and high capacity. Devices equipped with hybrid SSDs can be utilized to cache files from the network for performance improvement. However, this paper finds an interesting observation, that is, the efficiency of hybrid SSDs is significantly degraded instead of improved when too much data is cached. This is because the internal mode switching between different types of flash memory is affected by the device utilization. This paper proposes a dynamic file cache optimization scheme for hybrid SSDs, DFCache, which optimizes the device’s efficiency and limits unreasonable space consumption. DFCache includes two key ideas, dynamic cache space management, and intelligent cache file sifting. DFCache is implemented in Linux kernel and tested under real hybrid SSDs. Experimental results show that the I/O performance outperforms the state-of-the-art by up to 3.7x.

Capacitance extraction and power grid (PG) analysis for IC design involve large-scale numerical simulation problems. As the process technology becomes more complicated and design margin is shrinking, the capacitance field solver and power-grid matrix solver with high accuracy and capability for handing large and complex structure are highly demanded. In this invited paper, we present recent application of statistical and AI methods in these two fields. The Markov-chain model and relevant analysis are presented for developing an efficient technique for handling conformal dielectrics in the floating random walk based capacitance extraction. Then, two approaches reducing the computational cost of a domain decomposition based power-grid solver are presented. One employs supervised machine learning while the other is inspired by the A*-search algorithm.

A machine-learning-driven approach for matrix ordering is proposed for power grid analysis based on domain decomposition. It utilizes support vector machine or artificial neural network to learn a classifier to automatically choose the optimal ordering algorithm, thereby reducing the expense of solving the subdomain equations. Based on the feature selection considering sparse matrix properties, the proposed method achieves superior efficiency in runtime and memory usage over conventional methods, as demonstrated by industrial test cases.

Accurately estimating the rare failure rates for nanoscale circuit blocks (e.g., static random-access memory, D flip-flop, etc.) is a challenging task, especially when the variation space is high-dimensional. In this paper, we propose a novel scaled-sigma sampling (SSS) method to address this technical challenge. The key idea of SSS is to generate random samples from a distorted distribution for which the standard deviation (i.e., sigma) is scaled up. Next, the failure rate is accurately estimated from these scaled random samples by using an analytical model derived from the theorem of “soft maximum.” Our proposed SSS method can simultaneously estimate the rare failure rates for multiple performances and/or specifications with only a single set of transistor-level simulations. To quantitatively assess the accuracy of SSS, we estimate the confidence interval of SSS based on bootstrap. Several circuit examples designed in nanoscale technologies demonstrate that the proposed SSS method achieves significantly better accuracy than the traditional importance sampling technique when the dimensionality of the variation space is more than a few hundred.

Accurately estimating the rare failure rates for nanoscale circuit blocks (e.g., SRAM, DFF, etc.) is a challenging task, especially when the variation space is high-dimensional. In this paper, we propose a novel scaled-sigma sampling (SSS) method to address this technical challenge. The key idea of SSS is to generate random samples from a distorted distribution for which the standard deviation (i.e., sigma) is scaled up. Next, the failure rate is accurately estimated from these scaled random samples by using an analytical model derived from the theorem of “soft maximum”. Several circuit examples designed in nanoscale technologies demonstrate that the proposed SSS method achieves superior accuracy over the traditional importance sampling technique when the dimensionality of the variation space is more than a few hundred.