In current cryogenic temperature sensor (cryo-TS) systems, the sensing front-end and readout circuits typically operate in cryogenic and room-temperature environments, respectively. This paper proposes a scheme to integrate both the front-end devices and readout circuits of cryo-TS within the cryogenic environment to achieve lower noise, digital fan-out of temperature information, and cost reduction. We employed the silicon-germanium (SiGe) heterojunction bipolar transistors (HBT), which demonstrated excellent linearity and current gain even at cryogenic temperatures, as the sensing front end of the cryo-TS and a Zoom-ADC as its readout circuits. A redundancy bit is introduced in the cryogenic readout ADC to avoid temperature misjudgment. The design methodology and key considerations for implementing cryogenic readout analog circuits are presented. Implemented in a 65 nm CMOS process, the cryo-TS achieved a 1-point-trimmed (at 40 K) inaccuracy of ±0.54 K ($\boldsymbol {3\sigma }$) from 4 K to 70 K under a supply current of 22.13$\mu A$.

Cryo-CMOS IC for quantum applications, proposed for tens of years, are designed to control quantum processors operating at cryogenic temperatures (CTs). The reference circuits play a significant role in quantum controllers, providing a relatively stable biasing for analog and radio frequency (RF) circuit blocks. Based on a literature review, we discovered that achieving high-accuracy reference voltage or current at CTs is challenging due to the unstable temperature characteristics of complementary metal-oxide-semiconductor (CMOS), bipolar junction transistor (BJT), or resistors in the general CMOS process at CTs. Therefore, certain specialized device structures, such as dynamic threshold MOS (DTMOS), can be employed within the bulk CMOS process. Alternatively, BJT and other devices found in specific processes, such as silicon-germanium (SiGe) and fully depleted silicon on insulator (FD-SOI) CMOS, can achieve adaptive temperature compensation. This paper provides a succinct overview of several fundamental structures and common research hot spots about the reference voltage circuits, and then assesses their suitability for CT circuit design, considering the reliability of devices in bulk CMOS, FD-SOI CMOS, and SiGe process. Finally, the paper summarizes the types of cryo-temperature reference circuits and offers an overview and comparison of them.