Demo Data from EDBT 2026 / reviewers in the wild / expert
Ahmed A. Kamal
dblp:139/6029
· DBLP profile ↗
3ranked-venue papers
3as first author
0since 2021 · last 1981
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-authorHuman-computer interaction and ubiquitous computing · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Integrated circuit design · 40% Hardware accelerators and domain-specific architectures · 20% Processor architecture and microarchitecture · 20% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › analog and mixed-signal circuits
analog circuit design |
0.0 | 1 | 1972 | Analysis and Compensation of High-Speed Electronic Analog-Computer Errors · IEEE Trans. Computers 1972 |
Integrated circuit design › analog and mixed-signal circuits
analog computer |
0.0 | 1 | 1972 | Analysis and Compensation of High-Speed Electronic Analog-Computer Errors · IEEE Trans. Computers 1972 |
Processor architecture and microarchitecture
arithmetic unit |
0.0 | 1 | 1972 | High-Speed Multiplication Systems · IEEE Trans. Computers 1972 |
Hardware accelerators and domain-specific architectures
error compensation |
0.0 | 1 | 1972 | Analysis and Compensation of High-Speed Electronic Analog-Computer Errors · IEEE Trans. Computers 1972 |
Methods — techniques the papers use, named apart from their topics
perturbation analysis · 0.0comparative analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1981 | Multistage Clustering: An Efficient Technique in Socioeconomic Field ExperimentsabstractA multistage clustering methodology to partition large developing societies into a collection of communities with distinct characteristics is introduced. The methodology is based on multiple attributes expressing the socioeconomic status. In the context of our approach, no index of development is needed. An excellent application of the developed methodology lies in investigating the telecommunication needs for rural development in Egypt. The merits of our approach are reflected in overcoming the data inavailability on the village level and providing for an appropriate size of communities for field experimentation and analysis. An additional benefit is that the intricate sampling problem is indirectly solved. Ahmed A. Kamal, Saad M. Alyeid, Magdi Sadek Mahmoud |
IEEE Trans. Syst. Man Cybern. | 1 |
| 1972 | Analysis and Compensation of High-Speed Electronic Analog-Computer ErrorsabstractThe bandwidth limitations of the practical analog-computer units lead to dynamic errors in the computer solution. These errors can be represented either as a slight shift in the root positions of the system characteristic equation or as perturbations in the constant coefficients of the differential equation under solution. In this note, the authors report a unified approach to combine these two representations of dynamic errors and also show that these errors can be compensated for by setting the system after initial perturbations in its constant coefficients and in its driving functions have occurred. The approach is generalized for a system of simultaneous linear differential equations with constant coefficients. This technique will be of value in achieving a reasonable degree of accuracy with relatively inexpensive analog-computer components, and in extending the range of operating frequencies for a certain specified accuracy. Ahmed A. Kamal, A. K. El-Sherif |
IEEE Trans. Computers | 1 |
| 1972 | High-Speed Multiplication SystemsabstractLarge-scale scientific computers are characterized by having a high ratio of computing requirements to the input-output requirements. Thus the speed of arithmetic operations should be of prime importance in this group of digital computers. In this note a mathematical formula is derived to determine the multiplication time obtained by each of the known high-speed multiplication techniques. Then a comparative analysis is performed to show the amount of speed improvement resulting from each technique and the influence of the different factors affecting speed. Ahmed A. Kamal, M. A. N. Ghannam |
IEEE Trans. Computers | 1 |