Most of the Automatic Test Pattern Generation (ATPG) algorithms for digital circuits rely heavily on netlist description that comprises both network interconnect structure among logic gates and the functionality of each gate. The performance of an ATPG tool on a circuit-under-test (CUT) C is determined by the size of the test set T and its fault coverage (FC). Despite extensive research in the field of testing, the following question remains unanswered: Is the structure or the functionality of C dominant in determining FC of a test-set T for C? In this paper, we present empirical evidence in favour of the dominance of structure on FC by randomly selecting a logic gate from a synthesized netlist for C, and replacing it by a different type of gate. Our experiments provide an un-intuitive result that F C of a test-set T for C under the single stuck-at fault model remains nearly the same on other sibling circuits that have identical structure as of C but with different gate functionality, provided these have similar extent of fault redundancy. This observation supports the view that feeding structural information alone may suffice to train machine-learning models that are currently being used to expedite different problems of digital circuit testing and diagnosis.

Digital circuits are often prone to suffer from uncertain timing, inadequate sensor feedback, limited controllability of past states or inability of initializing memory-banks, and erroneous behavior of analog-to-digital converters, which may produce an unknown (${X}$) logic value at various circuit nodes. Additionally, many design bugs that are identified during the post-silicon validation phase manifest themselves as${X}$-values. The presence of such${X}$-sources on certain primary or secondary inputs of a logic circuit may cause loss of fault-coverage of a test set, which, in turn, may impact its reliability and robustness. In this paper, we provide a mechanism for predicting the sensitivity of${X}$-sources in terms of loss of fault-coverage, on the basis of learning only a few structural features of the circuit that are easy to extract from the netlist. We show that the${X}$-sources can be graded satisfactorily according to their sensitivity using support vector regression, thereby obviating the need for costly explicit simulation. Experimental results on several benchmark circuits demonstrate the efficacy, speed, and accuracy of prediction.

Although the modern automatic test pattern generation (ATPG) tools can efficiently produce near-optimal test sets with high fault-coverage for a circuit-under-test, a diagnostic test set (DTS), which is needed for fault localization, is much more challenging to construct. The DTS is used to analyze the responses of failing chips during manufacturing test for the purpose of identifying the root cause of observed errors. In this paper, a novel technique for selecting a powerful DTS for stuck-at faults from a pool of ATPG detection vectors is proposed. Unlike existing methods, this technique does not use any diagnostic test generation, circuit modification, or miter-based approach. It constructs a combinatorial cover of the pool to determine a test set with high diagnostic coverage (DC). Two variants of the covering algorithm are proposed based on this technique. The experimental results on several combinational and scan-based benchmark circuits demonstrate the effectiveness of our method in terms of the size of the DTS, DC, and CPU time.