Machine learning-guided optical proximity correction, called ML-OPC in this paper, has recently been proposed to alleviate long runtime of model-based OPC. ML-OPC using regression methods has been presented but with limited prediction accuracy. We propose neural network classifier-based OPC (NNC-OPC), in which a neural network classifier serves as a mask bias model. A few techniques are applied to enhance basic NNC-OPC: parameterization of layout segments using polar Fourier transform signals, dimensionality reduction through weighted principal component analysis, and sampling of training layout segments. Training segments are typically imbalanced over the range of mask biases, which may cause large prediction error for segments that appear less frequently. This is resolved by three techniques: 1) synthetic data generation; 2) class reorganization; and 3) an adaptive learning rate. Experiments with NNC-OPC with all techniques applied indicate that prediction error of mask bias and training time are reduced by 29% and 80%, respectively, compared to state-of-the-art ML-OPC with regression methods.

The remote center of motion (RCM) mechanism is a prominent candidate to aid bone drilling. The surgeon can simply place a drill with the RCM mechanism near the entry point to provide drill alignment with the target. Using this assistive mechanism for bone drilling improves drilling accuracy and reduces the complexity of bone drilling robotic systems. However, because most RCM mechanisms have been developed for laparoscopic surgery or needle insertion into soft tissue, they lack rigidity and are unsuitable for bone drilling. One of the most difficult and important surgical procedures in bone drilling is maintaining as well as guiding the orientation of the drill with respect to the target. This paper proposes an improved RCM mechanism in which a pair of linear actuators and a gearless arc-guide are employed to achieve high rigidity and resolution, which enable bone drilling. A vision-guided navigation system is also integrated into the proposed system to automatically guide the orientation. To verify that the proposed RCM mechanism has sufficient rigidity and targeting accuracy, a series of experiments was performed. The results obtained confirm that the proposed mechanism can maintain its tilting angle under up to 50 N, with a targeting error of approximately 0.28mm.

Line-end cut process has been used to create very fine metal wires in sub-14nm technology. Cut patterns split regular line patterns into a number of wire segments with some segments being used as actual routing wires. In sub-7nm technology, cuts are smaller than optical resolution limit, and a directed self-assembly lithography with multiple patterning (MP-DSAL) is considered as a patterning solution. We address cut mask optimization problem for MP-DSAL, in which cut locations are determined in such a way that cuts are grouped into manufacturable clusters and assigned to one of masks without MP coloring conflicts; minimizing wire extensions is also pursued in the process. Only a restricted version of this problem has been addressed before while we do not assume any such restrictions. The problem is formulated as ILP first, and a fast heuristic algorithm is also proposed for application to larger circuits. Experimental results indicate that the ILP can remove all coloring conflicts, and reduce total wire extensions by 93% on average compared to those obtained by the restricted approach. Heuristic achieves a similar result with less than 1% of coloring conflicts and 91% reduction in total wire extensions.

Guide-patterns (GPs) are critical to the construction of contacts and vias in directed self-assembly (DSA) lithography. Simulations can be used to verify GPs, but runtime is excessive. Instead, we categorize the shapes of GPs using a small number of geometric parameters. Then a verification function is built to predict whether a GP will produce the required contacts, as follows: a vector in parameter space is constructed to represent each GP in a test set; the acceptability of each GP is then assessed by DSA simulation, and each vector is tagged “good” or “bad” accordingly; next, the parameter space is deformed to convert a radial distribution into one in which the good and bad vectors can be separated by a hyper-plane, which finally becomes the verification function. We also show how to reduce the dimensionality of the parameter space by principal component analysis, and how to generalize the geometric description of GPs to allow different types of GP to be verified in a uniform fashion. The proposed GP verification is demonstrated in 10 nm technology.

Modern standard cells contain intercell margins at the left and right ends for better lithography. We introduce defect probability, which is the probability that a lithography defect occurs if the margins between two adjacent cells are missing. Computing the defect probability of all cell pairs is impractical due to lengthy lithography simulations and huge number of cell pair combinations. Two approximate methods are employed to make this computation possible: reducing the range of optical proximity correction and grouping cell pairs of similar geometry at the cell boundary. We also present how the cell layout can be modified for a lower defect probability with no impact on the cell electrical parameters. Defect probability is applied to two physical design optimization problems. In the automatic placement, we consider that all cells are initially without margins. We want to locate two cells adjacent if their defect probability is zero (or negligibly small) or insert margins in between; this is achieved using the average defect probability as one of the cost terms of the placement. Experiments in 28-nm commercial library demonstrate an 8% reduction in the area with a 4% shorter wirelength. In the second application, we assume that the standard placement using cells with margins have been performed. We want to identify redundant margins that can be removed while the defect probability is kept zero. We take a step forward and shuffle the location of a few consecutive cells in the same row so that more redundant margins are identified. Once all the redundant margins are removed, newly created whitespace is distributed to reduce routing congestion in highly congested areas. Experiments indicate a 48% reduction in the number of overflow routing grids.

In directed self-assembly lithography (DSAL), a mask contains the images of guide patterns (GPs), which are patterned on a wafer through optical lithography; the wafer then goes through DSA process to pattern contacts. Mask design for DSAL, which is the opposite of the above processes, consists of two key steps, inverse DSA and inverse lithography, which we address in this paper. In inverse DSA, we progressively refine GPs until they produce target contacts as closely as possible. GP is defined as a function of a few geometry parameters, and how sensitive the contacts are to the parameters are calculated which then guides how much the GP should be refined. In inverse lithography, mask is progressively refined so that target GPs are produced. Mask is defined by pixel values and their gradient guides the direction that the mask should be refined. There are too many pixels for gradient calculation; the method to approximate calculation is proposed. Inverse DSA and inverse lithography are extended to handle process variations. We modify basic inverse lithography so that the resulting mask becomes less sensitive to lithography variations; basic inverse DSA is modified so that it provides the way this sensitivity can be checked.

In sub-7nm technology, the size and pitch of vias are much smaller than optical resolution limit, and directed self-assembly lithography with multiple patterning technology (MP-DSAL) has been proposed as a solution. In MP-DSAL, vias that are close are clustered and patterned together via DSAL process, and via clusters that are close are printed using different masks via MP. Redundant vias, which are typically used for better via manufacturability, should be inserted very carefully in MP-DSAL because some redundant vias may cause large and complex via clusters, which are undesirable in DSAL; some other redundant vias may cause mask assignment of via clusters impossible, often called MP coloring conflict.

Crosslinks may be inserted in a few clock tree nodes to reduce on-chip variation induced clock skew, simply called OCV skew. A change in clock transition and clock latency should be accurately estimated and be reflected in crosslink insertion algorithm, which we study. Fast estimation of OCV skew is important, which we also address. Crosslink insertion problem is modeled into a graph, and is solved through integer linear programming (ILP) as well as a fast heuristic. Experiments in 28-nm technology indicate that maximum OCV skew is reduced by 44% and 35%, on average, by ILP and heuristic algorithm, respectively.

In directed self-assembly lithography (DSAL), an inter-cell cluster of contacts, which crosses the boundary of cells, is more likely to cause patterning failure because corresponding guide pattern (GP) has not been verified beforehand. All forms of inter-cell clusters can systematically be identified and grouped, which allows us to define DSA defect probability when two arbitrary cells are placed side by side. We then address post-placement optimization, in which some cells are flipped and some cells are swapped with their adjacent cells so that the number of whitespaces inserted in between cell pairs of high defect probability is minimized. Experiments with a few test circuits demonstrate 11% increase of placement density, on average, with no expected DSA defects.

In DSAL, contact holes are indirectly formed through guide patterns (GPs). Thus the integrity of GPs is very important, in particular when GP shape is large and complex. The limitation in GP shape calls for careful consideration in physical design stage. In mask optimization, synthesizing ideal GP shape and verifying whether synthesized GP is correct are important but difficult problem. Some challenges in physical design and mask optimization are reviewed in this paper with possible solutions.

Conventional standard cells contain extra space, called inter-cell margin, to prevent potential defects caused by lithography process. Margin is indeed necessary between some cell pairs, but there are also lots of cell pairs that do not yield any defects (or have very low probability of defects) when they are placed without margin. We address a new placement problem using standard cells without inter-cell margin. Placement should be done such that defect probability is made as small as possible while standard objectives such as wirelength is also pursued. The key in this approach is efficient computation of defect probabilities of all cell pairs and arranging them as a table that is referred to by a placer. We study how the cell pairs can be grouped by examining similar patterns along cell boundary, which greatly reduces the number of defect probability computation. The proposed placement method was evaluated on a few test circuits using 28-nm technology. Chip area was reduced by 10.8% on average with average and maximum defect probability kept below 0.4% and 4.1%, respectively.

Mesh clock network is very effective at reducing clock skew. But mesh causes a large increase of power consumption, in particular due to shorted buffers. We first analyze the short-circuit power consumption of the mesh clock network. It is observed that skew distribution of premesh tree is important in determining the amount of short-circuit power. We then propose a new clock buffer, which practically eliminates short-circuit current in a mesh network. Experiments on a few test circuits using 40-nm technology indicate that clock power consumption is reduced by 13.0% on average with 4.8% of area increase; this can be compared to buffer sizing, which only achieves 5.6% saving of power.