Multi-tier computation offloading is crucial to address capacity constraints and improve flexibility for mobile devices. However, existing research on multi-layer computing offloading faces challenges like inefficient resource utilization and poor scalability, particularly in handling diverse computational tasks. To address these challenges, this paper proposes a distributed resource allocation and mixed task offloading framework for end-edge-cloud collaborative systems that support partial and full task offloading modes. First, we propose a three-tier network computing architecture and formulate a task-offloading utility maximization problem by jointly optimizing mixed task-offloading and resource allocation. The proposed problem is a mixed integer nonlinear program (MINLP), which we solve by decomposing it into two subproblemsresource allocationandtask offloading. Edge computing resources and bandwidth allocation can be independently optimized at each edge node with a fixed task offloading strategy. Cloud computing resource allocation, while convex, involves a global constraint, which we solve in a decentralized manner using a multi-agent optimization approach. Then, we propose a joint task offloading and resource allocation optimization algorithm, CNO-TORA, to obtain the solution to the formulated problem. The algorithm is supported by strong theoretical guarantees and is almost surely convergent to a globally optimal solution. Experimental results on a real dataset demonstrate that our algorithm is scalable to large-scale networks and outperforms baselines, achieving improvements in average system utility ranging from 4.01%-28.15%.

Deep learning methods have achieved state-of-the-art performance in industrial fault diagnosis within the supervised learning paradigm. However, annotated data are scarce in industry, which can lead to overfitting and hinder their application. To address this issue, this article proposes a semisupervised learning framework that leverages self-supervised learning on abundant unlabeled data and supervised learning on limited labeled data simultaneously. Self-supervised learning captures inherent evolutionary dynamics, while supervised learning focuses on discriminative features. Specifically, a cross-prediction task on two augmented views of unlabeled data is devised using contextual representation. These contextual representations are used to construct a relational graph of unlabeled samples, which is then aligned with the corresponding logits graph. By facilitating interactions between the two tasks, the proposed framework achieves efficient fault diagnosis. Experiments on the Tennessee Eastman process and three-phase flow Facility datasets demonstrate the superiority of the proposed framework over other label-efficient methods.

Time-series anomaly detection plays a crucial role in industrial fault detection. Most existing studies follow either an unsupervised setting, which is prone to false alarms, or a supervised setting, which is time-consuming and labor-intensive. To address these limitations, we adopt an innovative weakly supervised paradigm for industrial fault detection, where segment-level labels are provided during training, while point-level predictions are made during inference. Within this paradigm, we propose an innovative$C$-ary tree-based multi-instance learning (MIL) framework. First, the entire time series is represented as a$C$-ary tree, where nodes representing subsequences of different lengths are treated as instances in the MIL framework. This design allows for the detection of both point and collective anomalies. Second, to detect out-of-distribution (OOD) anomalies that are not visible during training, we develop a vector quantization module to memorize regular historical patterns. OOD anomalies are then detected when they show significant discrepancies from all memorized patterns. Finally, we enhance the MIL framework with an attention-based pooling mechanism that allocates greater focus on anomalous instances, further improving detection performance. To validate the effectiveness of our method, we conduct experiments on four real-world industrial time-series datasets. The results show that our method outperforms existing approaches by at least 6.01% in AUROC under weak supervision.

Time series anomaly detection (TSAD) plays a vital role in various domains such as healthcare, networks and industry. Considering labels are crucial for detection but difficult to obtain, we turn to TSAD with inexact supervision: only series-level labels are provided during the training phase, while point-level anomalies are predicted during the testing phase. Previous works follow a traditional multi-instance learning (MIL) approach, which focuses on encouraging high anomaly scores at individual time steps. However, time series anomalies are not only limited to individual point anomalies, they can also be collective anomalies, typically exhibiting abnormal patterns over subsequences. To address the challenge of collective anomalies, in this paper, we propose a tree-based MIL framework (TreeMIL). We first adopt an N-ary tree structure to divide the entire series into multiple nodes, where nodes at different levels represent subsequences with different lengths. Then, the subsequences’ features are extracted to determine the presence of collective anomalies. Finally, we calculate point-level anomaly scores by aggregating features from nodes at different levels. Experiments conducted on seven public datasets and eight baselines demonstrate that TreeMIL achieves an average 32.3% improvement in F1-score compared to previous state-of-the-art methods. The code is available at https://github.com/fly-orange/TreeMIL.

Artificial neural networks (ANNs) have been widely used for tasks like electricity theft detection (ETD) in smart meters. However, due to the subtle mechanisms and inherent opaque characteristics, ANNs are vulnerable to attacks. Although this attack surface poses significant risks, it has been largely overlooked in industrial scenarios. To alert the widespread adoption of industrial intelligence, this article studies the impact of backdoor attacks in ETD for the first time and proposes a feature attention distillation (FAD) defense. First, the attack surface in current model training pipeline is analyzed, and the adversaries can embed malicious backdoors for specific triggers to escape ETD. Then, six prevalent ANN-based models are tested and the adversaries can bypass the backdoored ETD models with success rates over 90.53%, which would inevitably bring huge losses to electricity companies. We further argue that the electricity companies can mitigate such attacks when noticing the abnormal nontechnical loss. A novel FAD defense that aligns the intermediate feature maps between fine-tuned and backdoored models is proposed, which can eliminate backdoors more efficiently with few resources compared with two classic defenses. The average attack success rate can drop by 90.71% with slight impacts on ETD performance. This work sheds light on a novel but perilous attack surface, and raises a warning for the wide adoption of artificial intelligence in smart measurement scenarios.

Traffic incident detection is a critical task within traffic monitoring systems, enabling on-the-fly alerts for emergency actions. Numerous efforts have been made to detect and localize traffic incidents using data recorded by inductive loop detectors. However, they only focus on the node-level incidents that happen within the surveillance areas and ignore the edge-level ones that take place outside of these areas. In this paper, we propose to detect both kinds of incidents simultaneously based on the sparsely distributed sensors. An important challenge is how to explicitly model the edge status and detect this kind of incidents. Additionally, capturing complex relationships among traffic dynamics, road locations, and temporal information is non-trivial. In this paper, we first describe the traffic dynamics by a fine-grained graph where the sensor range is designed as a hyper-parameter to control the coverage boundaries. Then, we propose an Edge-and Node-aware Dual AutoEncoder (ENDAE), where the correlations are decoupled into inter-nodes, inter-series and inter-attribute parts, which are further captured via node encoder, temporal encoder and attribute encoder, respectively. Furthermore, the reconstruction errors are calculated for node-level and edge-level event detection separately. The overall method is evaluated based on two real-world datasets from Bay Area and Los Angeles in California. ENDAE surpasses all the state-of-the-art method in both kinds of incidents, with at least 12.5% improvement in recall and 18.5% decrease in delay. Notably, for edge-level incidents, ENDAE achieves double the recall of the previous SOTA methods.

Data-driven fault diagnosis for critical industrial processes has exhibited promising potential with massive operating data from the supervisory control and data acquisition system. However, automatically extracting the complicated interactions between measurements and subtly integrating them with temporal evolutions have not been fully considered. Besides, with the increasing complexity of industrial processes, accurately locating fault roots is of tremendous significance. In this article, we propose an unsupervised spatial-temporal aware graph encoder–decoder (STAGED) model for industrial fault diagnosis. First, the high-dimensional measurements are constructed as a weighted graph to depict the complicated interactions. Then, the graph convolutional network, long short-term memory network and attention mechanism are applied to learn a comprehensive representation for multiseries. To enforce the model to better capture the temporal evolution, the dual decoder that performs reconstruction and prediction tasks simultaneously is adopted with a well-designed comprehensive loss function. By learning the spatial-temporal evolutions of datasets, faults can be diagnosed and located at a fine-grained level based on reconstruction deviations. To verify the performance of STAGED, experiments on the Cranfield three-phase flow facility and secure water treatment datasets are implemented and the results indicate that it can provide insight into fault evolution and accurately diagnose faults.

The emergence of electric vehicles promotes the development of Internet of Vehicle (IoV). However, there are a series of security problems to be solved in the IoV. Firstly, how to allow vehicle users to find the nearest non-queuing charging pile without detours is a challenge. Secondly, applications in the IoV are delay-sensitive, while high communication delays caused by security mechanisms would bring serious consequences to vehicles. Thirdly, the verifiability and fairness between charging and payment are difficult to be guaranteed. Aiming at the efficiency and security problems of the charging service in the IoV, this paper proposes a blockchain-based intelligent and fair IoV charging service system. According to the multi-factor constraints between vehicles and charging piles, a multi-factor IoV branch and bound algorithm is proposed to intelligently recommend charging piles for vehicles and maximize the overall energy saving. We propose the cross-area consensus protocol to achieve low latency in vehicle communication. In addition, we ensure the fairness between charging and payment through a payment channel protocol based on verifiable encrypted signatures. Finally, we implement the proposed scheme, and we put the project prototype on an open source platform is available at:https://github.com/chenruonan/blockchain-based-intelligent-and-fair-IoV-charging-service-protocol. The experimental results demonstrate the low latency and energy-saving advantages of our proposal. When the payment is executed 250 times, the delay of our proposal is only 1.54% of the normal on-chain payment time.

The constraints of communication channel resources and control energies always lie in real networks, which bring large error and cause adverse affects on system performance, ultimately. To address these limitations, in this article, a distributed event-triggered impulsive control strategy for the consensus problem of fractional-order multiagent networks (FOMANs) is investigated. By collecting the local instantaneous access information, the distributed tracking algorithm with a novel triggering condition is proposed, which is available for both linear and nonlinear systems. Combining with general quadratic Lyapunov stability method and discontinuous control theory, the sufficient conditions of consensus in terms of gain parameter and impulsive interval are derived. Furthermore, the minimal length of interevent is proven to be strictly greater than zero, which guarantees the nonexistence of Zeno-behavior in the closed-loop system. In addition, the implementation of the fractional order algorithm, the quantitative relationship between fractional order$\alpha $or parameter$a$in the triggering function, and the number of event-triggered impulsive instants are discussed. At the end of this article, two illustrative examples with numerical and circuit simulations are provided to validate the effectiveness of above results.

We focus on a hardware implementation of the concatenated forward error-correction (FEC) decoder defined in 400ZR implementation agreement to provide a throughput of 400 Gbps over fiber-optical communication links. We propose a soft-input hard-output low-complexity decoding algorithm for the inner Hamming code. We demonstrate that the algorithm leads to an efficient hardware design with low silicon area and power dissipation. We then propose a hardware implementation architecture of the outer staircase decoder. It features a highly optimized low-power implementation of Bose-Chaudhuri-Hocquenghem (BCH) component decoders and the staircase decoder memory that can be efficiently accessed by either vertical or horizontal component decoders. Finally, we analyze the hardware implementation of the entire 400ZR decoder and investigate the trade-off in terms of power, area, and speed, that results from the inner/outer decoder concatenation and is dictated by the bit-error rate at the output of the inner decoder.

This brief presents a VLSI architecture of a high-throughput, low-latency, and power staircase forward error correction (FEC) encoder. The designed encoder achieves low latency and memory overhead by splitting the parity generation matrix and precomputing partial parity bits for the next staircase block while generating the current staircase block. The proposed encoder is designed with a multistage pipelined architecture that enables high efficiency in terms of throughput and area. Using 65-nm CMOS technology, the synthesized encoder achieves 432 Gb/s when operating at 909 MHz, with the power consumption of 323 mW.

In high definition (HD) video coders, huge memory access bandwidth is the major throughput bottleneck. Lossless embedded compression is an efficient solution to alleviate the bandwidth burden, in which image are compressed before writing into local memory and decompressed after retrieving from local memory. This study proposes a hardware‐oriented lossless image compression algorithm, supporting block and line random access flexibly for adapting diverse hardware video codec architectures. The major contributions are characterised as follows. First, block or pixel‐level adaptive prediction is proposed to fully utilise the image spatial correlation by employing adaptive mode decision. Second, multiple‐range semi‐fixed (SF) variable length coding (VLC) is employed to describe the prediction residue, and adaptive block size selection is employed for SF VLC to fully utilise the statistical redundancy. In addition, Huffman VLC is further employed to represent the control syntax elements. Third, four‐stage pipeline hardware architecture is proposed to implement the proposed algorithm. Simulation results show that the proposed algorithm achieves competitive rate compression performance compared with reference algorithms. The proposed hardware architecture is verified supporting real‐time processing for quad‐HD videos at the frequency of 166 MHz. The proposed work achieves reducing memory access bandwidth by ∼55.2%, which is useful for hardwired video coding.

FPGA and ASIC are suitable platforms for high definition video encoder implementation. Efficient video encoder VLSI architecture design suffers from several challenges and multiple target performance trade-off. Algorithm and hardware architecture are supposed to be jointly designed for multiple target performance trade-off. How to evaluate the performance, accounting for multiple target performance parameters, is one important problem for algorithm and architecture joint design. In this paper, we propose measure methods for multiple target performance parameters for VLSI architecture design, and then propose a novel multiple-target performance evaluation model. The performances of the prevalent H.264/AVC encoder architectures are evaluated with the proposed model. This work is meaningful for algorithm and architecture joint optimization.