A single-ISA heterogeneous multi-core processor(HMP) [2], [7] is comprised of multiple core types that all implement the same instruction-set architecture (ISA) but have different microarchitectures. Performance and energy is optimized by migrating a thread's execution among core types as its characteristics change. Simulation-based studies with two core types, one simple (low power) and the other complex (high performance), has shown that being able to switch cores as frequently as once every 1,000 instructions increases energy savings by 50% compared to switching cores once every 10,000 instructions, for the same target performance [10]. These promising results rely on extremely low latencies for thread migration. Here we present the H3 chip that uses 3D die stacking and novel microarchitecture to implement a heterogeneous multi-core processor (HMP) with low-latency fast thread migration capabilities. We discuss details of the H3 design and present power and performance results from running various benchmarks on the chip. The H3 prototype can reduce power consumption of benchmarks by up to 26%.

Three-dimensional (3-D) stacking of integrated circuits (ICs) using through-silicon-vias (TSVs) is a promising integration platform for next-generation ICs. Since TSVs are not fully accessible prior to bonding, it is difficult to test the combinational logic between scan flip-flops and TSVs at a prebond stage. In order to increase testability, it has been advocated that wrapper cells (WC) be added at both ends of a TSV. However, a drawback of WC is that they incur area overhead and lead to higher latency and performance degradation on functional paths. Prior work proposed the reuse of scan cells to achieve high testability, thereby reducing the number of WC that need to be inserted; however, practical timing considerations were overlooked and the number of inserted WC was still high. We show that the general problem of minimizing the WC is equivalent to the graph-theoretic minimum clique-partitioning problem, and is therefore NP-hard. We adopt efficient heuristic methods to solve the problem and describe a timing-guided and layout-aware solution. We evaluate the heuristic methods using an exact solution technique based on integer linear programming. We also present design-for-test optimization technique to leverage the reuse-based method during post-bond testing. Results are presented for 3-D-stack implementations of the ITC'99 and the OpenCore benchmark circuits.

Single-ISA heterogeneous multi-core processors are comprised of multiple core types that are functionally equivalent but microarchitecturally diverse. This paradigm has gained a lot of attention as a way to optimize performance and energy. As the instruction-level behavior of the currently executing program varies, it is migrated to the most efficient core type for that behavior.