Mobile devices have become the most important devices in our life. However, they are limited in battery capacity. Therefore, low-power computing is crucial for their long lifetime. A spin-transfer torque RAM (STT-RAM) has become emerging memory technology because of its low leakage power consumption. We herein propose MH cache, a multi-retention STT-RAM-based cache management scheme for last-level caches (LLC) to reduce their power consumption for mobile hardware rendering systems. We analyzed the memory access patterns of processes and observed how rendering methods affect process behaviors. We propose a cache management scheme that measures write-intensity of each process dynamically and exploits it to manage a power-efficient multi-retention STT-RAM-based cache. Our proposed scheme uses variable threshold for a process’ write-intensity to determine cache line placement. We explain how to deal with the following issue to implement our proposed scheme. Our experimental results show that our techniques significantly reduce the LLC power consumption by 32% and 32.2% in single- and quad-core systems, respectively, compared to a full STT-RAM LLC.

Multi-core processors with shared L2 caches can improve performance and integrate several functions of real-time systems on a single chip. However, tasks running on different cores increase interferences in the shared L2 cache, resulting in more deadline misses and, consequently, worse quality of real-time tasks. This is mainly because of the blind sharing of the L2 cache by multiple tasks running on different cores.We propose a novel performance-controllable shared L2 cache architecture that can alleviate these problems. First, our proposed L2 cache architecture is made to be aware of instructions/data belonging to real-time tasks by adding a real-time indication bit to each L2 cache block. Second, it can control the performance of real-time tasks and non-real-time tasks. Our experimental results show that our proposed L2 cache architecture reduces more deadline misses of real-time tasks than the conventional L2 cache architecture and partitioning schemes.