A high-speed, low-figure-of-merit capacitive floating level shifter (CF-LS) for high-side bootstrapped gate drivers is presented. The design integrates a feedback discharge control (FBDC) for enhanced$V {_{\text {SW}}}$dV/dt (SRSW) immunity and combines a mismatch reduction circuit (MMRC) with a common-mode blanking pulse (CMBP) to block common-mode (CM) signals with mismatch. Fabricated in a 0.75-$\mu $m STMicroelectronics bipolar-CMOS-DMOS (BCD) process, the proposed CF-LS occupies 0.048 mm2with the core area being 0.026 mm2, making it highly compact and integration-friendly. It achieves a propagation delay ($T {_{\text {P}}}$) of 1.525 ns and transition energy ($E_{T}$) of 29.77 pJ at 40 V, both of which remain approximately constant across the$V {_{\text {SW}}}$sweep from 0 to 40 V, while maintaining measured SRSWimmunity of up to 20 V/ns and mismatch tolerance up to 30%. Compared to recent works, the design offers a$2\times $improvement in figure-of-merit2 (FoM2), achieving 2.68 ns$\cdot $pJ/$\mu $m${^{{3}}} \cdot $V at bootstrap supply ($V {_{\text {BS}}}$) of 5 V, and$3\times $improvement when supplied at 3.3 V. The CF-LS has been comprehensively validated both as a standalone circuit and when integrated within a dc–dc buck converter, making it a highly robust, efficient, and versatile solution for high-frequency power management systems operating up to 55 MHz.

A high-speed low-figure-of-merit capacitive-coupled level shifter tailored for high-side bootstrapped gate drivers is presented. Key techniques include a Feedback Discharge Control (FBDC) for improved dV/dt Immunity, a MisMatch Reduction Circuit (MMRC) in combination with Common-Mode Blanking Pulse (CMBP) to block common-mode signals with improved mismatch tolerance. The level shifter is fabricated in a 0.75µm STMicroelectronics BCD process and covers a chip area of 0.048mm2. Experimental results demonstrate a Propagation delay (TP) of 1.525ns and Transition Energy (ET) of 29.77pJ at 40V, with a dV/dt immunity of up to 20V/ns. The level shifter achieves a figure-of-merit 2 (FoM2) of 2.68ns.pJ/um3.V, an improvement of 2x from the recent literature, and exhibits a mismatch tolerance of 20%. The design has been tested at a switching frequency (FSW) of up to 55MHz. The design is validated through standalone and integrated testing in a DC-DC buck converter.

In this paper, the problem of bit-errors recovery in JPEG2000 images transmission is addressed, with particular attention to errors in the high-frequency components. In the HL and LH sub-bands, differently from the LL band, interpolation based recovering results tend to be often ineffective when more than a few adjacent wavelet coefficients are missing. The solution proposed is then to apply a wavelet patch repetition procedure by predicting the similitude between the contour structure in the damaged area and its surroundings. To this aim, the correlation in the spatial structure, that is the contour information, existing between different sub-bands has been analyzed and exploited. Accordingly, the patch used to conceal the corrupted region is that obtained by minimizing a correlation measure with the spatial structure extracted from an adjacent not corrupted subband. Objective and subjective improvements have been obtained.