Presents an area-efficient register transfer level technique for gracefully degradable data path synthesis called phantom redundancy. In contrast to spare-based approaches, phantom redundancy is a recovery technique that does not use any standby spares. Phantom redundancy uses extra interconnect to make the resulting data path reconfigurable in the presence of any (single) functional unit failure. When phantom redundancy is combined with a concurrent error detection technique, error detection followed by reconfiguration is automatic. The authors developed a register transfer level synthesis algorithm that incorporates phantom redundancy constraints. There is a tight interdependence between reconfiguration of a (faulty) data path and scheduling and operation-to-operator binding tasks during register transfer level synthesis. They developed a genetic algorithm-based register transfer level synthesis approach to incorporate phantom redundancy constraints. The algorithm minimizes the performance degradation of the synthesized data path in the presence of any single faulty functional unit. The effectiveness of the technique and the algorithm are illustrated using high-level synthesis benchmarks.

We report a register transfer level technique for concurrent error detection and diagnosis in data dominated designs called Introspection . Introspection uses idle computation cyles in the data path and idle data transfer cycles in the interconnection network in a synergistic fashion for concurrent error detection and diagnosis (CEDD). The resulting on-chip fault latencies are one ten-thousandth (10 -4 ) of previously reported system level concurrent error detection and diagnosis latencies. The associated area overhead and performance penalty are negligible. We derive a cost function that considers introspection constraints such as (i) executing an operation on three disjoint function units for diagnosis and (ii) promoting function units to participate in at least one CEDD operation. We formulate integration of introspection constraints into the operation-to-operator binding phase of high-level synthesis as a weighted bipartite matching problem. The effectiveness of introspection and its implementation are illustrated on numerous industrial strength benchmarks.

Abs/rucf-Thii paper presents effisient reerscoding and reayntfs-is algorithms for cycle-time mirdmtition of rnrdtilevel tiplensentatimrs of synchronom finite state machines @Shfs)under a tied encoding length.me proposed technique is appficahle to both gate-level and technology independent synchmnom network rep~enfstimrs.We pr~ent two algorithm for identifying srsefulreencmfbrgs-one is based on Boolmn cube reprwentation apptieafrle to technology independent ayrrchmrsmssnetworks and tbe other employs recursive learning techniques appmpfiate for gate ne~.We show that the proposed XOtixNOR based reencadbsg technique mplores a sufficientlyrich set of encodings to identify implementations with smalIer cycle-times.The Boolwn and stmctural interpretations of reencoding are explored and ik relationship to isomorphic sequentially redundant faults is presented.We afso show that the reencoded circuit always has a vatid initial state and present a simple procedureto deriveiL The effectiveness of the proposedtechniqueis iUnstratedon a largeset of benchmarkcircuitswhichindfratman averagecycle-timeimprovement of 15.26%for a smallam overbcadof336Yaoverthat ofperfomsance~rivencombbsatfmsal logicoptimizafiom

Introspection, a zero-overhead binding technique during self-diagnosing microarchitecture synthesis is presented.Given a scheduled c ontrol data ow graph (CDFG) introspective binding exploits the spare c omputation and data transfer capacity in a synergistic fashion to achieve low latency fault diagnostics with near zero area overheads without compromising the performance.The resulting on-chip fault latencies are one ten-thousandth (10 4 ) of previously reported system level diagnostic techniques.A novel feature of the proposed t e chnique is the use of spare data transfer capacity in the interconnect network for diagnostics.

This paper presents Metamorphosis-a novel technique for optimal state assignment targeting multi-level logic implementations. We present an elegant matrix formulation and a graph partitioning based synthesis technique which permits both bit-constrained and unconstrained encoding of a symbolic finite state machine (FSM) represented initially with a one-hot code. Optimal state encoding is achieved by controlled retiming/re-encoding and resynthesis of the symbolic FSM. The synthesis is guided directly by the cost function (optimization criterion) rather than speculative estimates of the encoding heuristics on the final design cost. The technique is illustrated through performance driven synthesis of FSM and extensions to handle other cost metrics is outlined.

Phantom redundancy, an area-efficient technique for fabrication-time reconfigurability is presented. Phantom redundancy adds extra interconnect so as to render the resulting microarchitecture reconfigurable in the presence of any (single) functional unit failure. The proposed technique yields partially good chips in addition to perfect chips. A genetic algorithm is used to incorporate phantom redundancy constraints into microarchitecture synthesis. The algorithm minimizes tire performance degradation due to any faulty functional unit of the resulting microarchitecture. The effectiveness of the technique is illustrated on benchmark examples.