Guido De Sandre

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2ranked-venue papers
1as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 44% Embedded and real-time systems · 44% Memory systems · 13%

Topics — the 1 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › non-volatile memory
embedded flash memory
0.012003
A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory · DAC 2003
YearPublicationVenuePosition
2006 Full-range cellular neural networks and differential variational inequalities
abstract
We consider the full-range (FR) model of cellular neural networks (CNNs) in the ideal case where the neuron nonlinearities are hard-comparator functions with two unbounded vertical segments. The dynamics of FR-CNNs is rigorously analyzed by using theoretical tools from set-valued analysis and differential inclusions. The fundamental property proved in the paper is that FR-CNNs are equivalent to a special class of differential inclusions named differential variational inequalities. On this basis, a sound foundation to the dynamics of FR-CNNs is given, by establishing results on the existence and uniqueness of the solution starting at a given point, and on the existence of equilibrium points. Moreover, some fundamental results on trajectory convergence towards equilibrium points (complete stability) for reciprocal standard CNNs are extended to reciprocal FR-CNNs by using a generalized Lyapunov approach
Guido De Sandre, Mauro Forti, Paolo Nistri, Amedeo Premoli
ISCAS1
2003 A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory
abstract
A 1GOPS dynamically reconfigurable processing unit with embedded Flash memory and SRAM-based FPGA targets image-voice processing and recognition applications. Code, data and FPGA bitstreams are stored in the embedded Flash memory and are independently accessible through 3 content-specific, 64-bit I/O ports with a peak read rate of 1.2GB/s. The system is implemented in a 0.18um, 2PL-6ML CMOS Flash technology, chip area is 70mm2.
Michele Borgatti, Lorenzo Cali, Guido De Sandre, Benoit Forêt, David Iezzi, Francesco Lertora, Gilberto Muzzi, Marco Pasotti, Marco Poles, Pier Luigi Rolandi
DAC3