Previously, a new pipelinable PSTAR-RLS algorithm was developed. It was shown to be an effective alternative to the QRD-RLS algorithm when high-speeds are required. Using a folding technique, a 4-tap PSTAR-RLS algorithm was implemented on a single VLSI chip. All the operations in the chip are bit-level pipelined. With a 1.2 /spl mu/ CMOS technology this chip is expected to run at 100 MHz. Redundant number system based arithmetic operators were used for performance advantage. Apart from a wafer scale implementation, this is the first ever single chip ASIC implementation of a RLS adaptive filter.

The QR decomposition based recursive least-squares (RLS) adaptive filtering (referred to as QRD-RLS) algorithm is suitable for VLSI implementation since it has good numerical properties and can be mapped to a systolic array. Recently, a new fine-grain pipelinable STAR-RLS algorithm was developed based on scaled tangent rotation. The pipelined STAR-RLS algorithm, referred to as PSTAR-RLS, is useful for high-speed applications. The stability of QRD-RLS, STAR-RLS and PSTAR-RLS has been proved but the performance of these algorithms in finite-precision arithmetic has not yet been analyzed. The aim of this paper is to determine expressions for the degradation in the performance of these algorithms due to finite-precision. By exploiting the steady-state properties of these algorithms, simple closed-form expressions are obtained which depend only on known parameters. Since floating-point or fixed-point arithmetic representations may be used in practice, both representations are considered in this paper. The results show that the PSTAR-RLS and STAR-RLS algorithms perform better than the QRD-RLS especially in a floating-point representation. The theoretical expressions are found to be in good agreement with the simulation results.>

The performance of two commonly used linear models of associative memories, generalized inverse (GI) and correlation matrix memory (CMM) is studied analytically in the presence of a new type of noise (training noise due to noisy training patterns). Theoretical expressions are determined for the S/N ratio gain of the GI and CMM memories in the auto-associative and hetero-associative modes of operation. It is found that the GI method performance degrades significantly in the presence of training noise while the CMM method is relatively unaffected by it. The theoretical expressions are plotted and compared with the results obtained from Monte Carlo simulations and the two are found to be in excellent agreement.>

Achieving high speed in decision feedback equalizers (DFEs) is difficult because of the nonlinear decision directed adaptation. Recently, parallel DFE and extended LMS DFE algorithms were proposed for parallel implementation of DFEs. A new double-row DFE algorithm which outperforms the previous approaches is presented. Under the no error propagation assumption, this algorithm performs exactly like a serial DFE. The above three algorithms degrade drastically at high speeds and are more computationally expensive. Three additional novel parallel implementations of the DFE which lead to considerable hardware savings and avoid the coding loss of the former approaches are proposed. These new algorithms are referred to as the direct parallel, double-row DFE without weight correction, and improved block techniques. The first two algorithms give performance that is only slightly degraded as compared to the earlier methods. The improved block technique provides the best performance at higher speed.>