3D NAND flash memory is currently the mainstream storage medium due to high density and large capacity. However, the high raw bit error rate (RBER) poses challenges to data reliability. Low-density parity-check (LDPC) codes, known for strong error correction capabilities, are widely used to ensure data reliability. Traditional error correction schemes employ a single, fixed LDPC code, resulting in suboptimal performance–excess decoding overhead at low RBER and insufficient correction capability at high RBER. To address these limitations, we propose DyLDPC: a dynamic LDPC code with variable correction capability to improve decoding performance for 3D NAND flash memory. DyLDPC dynamically adjusts the error correction capability of LDPC codes based on the temporal and spatial variations of RBER in 3D NAND flash memory. Temporally, RBER increases with retention time and program/erase (P/E) cycles. Spatially, RBER varies across layers and pages. DyLDPC predicts RBER under varying conditions and allocates appropriate LDPC codes accordingly, effectively reducing ECC storage overhead, extending flash memory lifespan, and improving decoding efficiency. While ensuring data reliability, it optimizes error correction performance. Evaluations indicate that DyLDPC reduces decoding iterations by 8.1% and latency by 74% on average compared to static schemes. Additionally, using differentiated LDPC codes for most significant bit (MSB) and least significant bit (LSB) pages in multi-level cell (MLC) NAND further reduces LSB decoding latency by 27.8%.

This paper presents a 1-GS/s 7-bit 3-then-1 bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). To strike a good balance among the noise performance, power consumption, transistor size, and offset, a reconfigurable reference-embedded comparator is proposed. The comparator is first configured with 7 embedded reference voltages, which can complete the conversion of 3 bits in one cycle. The 3-bit/cycle comparator is then reconfigured to 1-bit/cycle in the last conversion cycle, with improved noise performance and reduced the offset mismatches between the seven latches. As a result, the ADC achieves relatively good precision with considerable power efficiency. A design example of 1-GS/s 7-bit SAR ADC in 40nm CMOS technology is presented. Simulation results show that the ADC achieves a spurious free-dynamic-range (SFDR) of 53.98 dB a signal-to-noise-and distortion ratio (SNDR) of 42.51 dB, with a figure-of-merit of 27.3 fJ/conv.-step.

High-density and reliable multilevel-cell (MLC) resistive random access memory (RRAM) is expected to meet the ever-increasing demand for on-chip weight storages in the intelligent edge devices. However, due to the device variations, many write-and-verify (WAV) iterations are usually required to program the RRAM cell, which causes high power consumption, long latency, and degradation on the memory lifetime. To address this issue, we propose a write–verify-free MLC RRAM macro for weight storage with 1) a cascode-current-mirror multibit write (CCM-MW) driver and 2) a nonbinary programming scheme (NB-PS) with a radix not greater than 2. A 180-nm 400-Kb RRAM test chip is demonstrated in silicon. For 2-bit-per-cell MLC storage, the value error rates can be reduced by 24.13% after introducing two redundant bits (RBDs). In addition, compared to the single-level cell (SLC) storage scheme, a 37.50% reduction in the number of cells can be achieved to store the ResNet-8 model with a 0.79% loss in inference accuracy without the need for WAV iterations.

Embedded redundant array of independent drives (eRAID) architecture was proposed for a high-capacity solid-state drive (SSD) controller, which applies an embedded redundant array of independent drives (RAID) engine to drive and manage an array of independent embedded multimedia card (eMMC) modules. However, the performance of its random access was limited by the eMMC’s uncontrollable timing during data stripping among the eMMC channels. This brief solves this issue using the nonvolatile memory express (NVMe) engine embedded in the controller and a reorganized buffer stripping mechanism. An SSD controller with peripheral component interconnect express (PCIe) Gen$3^{\ast} 4$Lane interface was designed to verify the capacity and performance, and it was manufactured into a silicon integrated circuit (IC) using a 55-nm semiconductor process. This architecture provides a prospective way to eliminate external dynamic random access memory (DRAM) buffers while maintaining a high random access speed.

The adaptive modulation is an important effective technique, which can be applied in the multiple-input-multiple-output (MIMO) system to achieve a high average spectral efficiency. In this paper, an adaptive minimum transmit power modulation scheme under constant data rate and fixed bit error rate (BER) for the spatial MIMO system is proposed. It adjusts the modulation order and allocates the transmit power to each spatial subchannel when meeting the user's requirements at the cost of minimum transmission power. Computer simulation results present the efficiency of the proposed scheme

A modified decision feedback equalizer (DFE) is proposed for efficient equalization of sparse channels with large delay echoes. This new structure can both avoid noise accumulation in large number of filter taps and reduce hardware implementation complexity effectively. Brief analysis about noise accumulation effects in large-scale equalizer and working mechanism description of this effective NRCR-DFE algorithm exhibit us where the performance gain lies. Simulation results show that this modified DFE has higher performance than the conventional ones and is quite fit for applications in high-speed systems like high definition television (HDTV) and broadband mobile communication.