Hyperspectral imaging is an excellent tool to remotely analyze the Earth from in-orbit devices. Satellites capture these images containing vast information about the ground pixels. To optimize storage and transmission speeds, compression is often performed onboard the satellite. To that end, algorithms such as the CCSDS 123.0-B-2 are implemented on FPGAs, enabling this process in an efficient and fast manner. Single-Event Upsets (SEU) are commonplace in this scenario, e.g. bit flips in the FPGA’s configuration memory which can catastrophically alter the algorithm’s output. In this paper, we propose a fault tolerance technique for this specific case. The compression core is checked periodically by running a golden model designed to excite the full internal datapath based on a synthetic image. A failure in this check will trigger a reconfiguration of the compression core. Results show better detection rates than Dual Modular Redundancy (DMR) at a fraction of the resource cost, proving this technique as a viable alternative. Furthermore, other algorithms with similar processing flows might benefit as well from this technique.

This paper proposes two approaches for reducing the impact of the error floor phenomenon when decoding quantum low-density parity-check codes with belief propagation based algorithms. First, a low-complexity syndrome-based linear programming (SB- LP) decoding algorithm is proposed, and second, the proposed SB-LP is applied as a post-processing step after syndrome-based min-sum (SB-MS) decoding. For the latter case, a new early stopping criterion is introduced to decide when to activate the SB- LP algorithm, avoiding executing a predefined maximum number of iterations for the SB-MS decoder. Simulation results show, for a sample hypergraph code, that the proposed decoder can lower the error floor by two to three orders of magnitude compared to SB-MS for the same total number of decoding iterations.

Due to the recent advances in new communication standards, such as 5G New Radio and beyond 5G, and in quantum computing and communications, new requirements for integrating processors into nodes have appeared. These requirements are meant to provide flexibility in the network to reduce operational costs and support diversity in services and load balancing. They are also designed to integrate both new and classical algorithms into efficient and universal platforms, execute specific operations, and attend to tasks with lower latency. Furthermore, some cryptographic algorithms (classical and post-quantum), which are essential to portable devices, share the same arithmetic with error-correction codes. For example, Advanced Encryption Standard (AES), elliptic curve cryptography, Classic McEliece, Hamming Quasi-Cyclic, and Reed-Solomon codes use GF(2^m) arithmetic. As this arithmetic is the basis of many algorithms, a versatile RISC-V Galois field ISA extension is proposed in this work. The RISC-V instruction set extension is implemented and validated using SweRV-EL2 1.3 on a Nexys A7 FPGA. In addition, a five-times acceleration is achieved for AES, Reed-Solomon codes, and Classic McEliece (post-quantum cryptography) at the expense of increasing the logic utilization by 1.27%.

This work presents the design of a very high throughput RS(255,239) decoder for a single data stream. Implementation results show that it is possible to reach 140 Gbps when implemented in a 90nm CMOS process. The proposed architectures are more area-time efficient than previously published high-throughput RS(255,239) decoders.

This paper presents a novel algorithm based on trellis min-max for decoding non-binary low-density parity-check (NB-LDPC) codes. This decoder reduces the number of messages exchanged between check node and variable node processors, which decreases the storage resources and the wiring congestion and, thus, increases the throughput of the decoder. Our frame error rate performance simulations show that the proposed algorithm has a negligible performance loss for high-rate codes with GF(16) and GF(32) and a performance loss smaller than 0.07 dB for high-rate codes over GF(64). In addition, a layered decoder architecture is presented and implemented on a 90-nm CMOS process for the following high-rate NB-LDPC codes: (2304, 2048) over GF(16), (837, 726) over GF(32), and (1536, 1344) over GF(64). In all cases, the achieved throughput is higher than 1 Gb/s.

Nonbinary LDPC codes outperform their binary counterparts in different scenarios. However, they require a considerable increase in complexity, especially in the check-node (CN) processor, for high-order Galois fields (GFs) higher than GF(16). To overcome this drawback, we propose an approximation for the trellis min-max algorithm that allows us to reduce the number of exchanged messages between the CN and the variable node compared with previous proposals from the literature. On the other hand, we reduce the complexity in the CN processor, keeping the parallel computation of messages. We implemented a layered scheduled decoder, based on this algorithm, in a 90-nm CMOS technology for the (837, 723) NB-LDPC code over GF(32) and the (1536, 1344) over GF(64), achieving an area saving of 16% and 36% for the CN and 10% and 12% for the whole decoder, respectively. The throughput is 1.07 and 1.26 Gb/s, which outperforms the state of the art of high-rate decoders with the high GF order from the literature.

A high-speed non-binary LDPC decoder based on Trellis Min-Max algorithm with layered schedule is presented. The proposed approach compresses the check-node output messages into a reduced set, decreasing the number of messages sent to the variable node. Additionally, the memory resources from the layered architecture are reduced. The proposed decoder was implemented for the (2304,2048) NB-LDPC code over GF(16) on a Virtex-7 FPGA and in a 90 nm CMOS process. Our implementation outperforms state-of-the-art NB-LDPC decoder implementations for both technologies, achieving a throughput of 630 and 965 Mbps, respectively.

Nonbinary low-density parity-check (NB-LDPC) codes have become an efficient alternative to their binary counterparts in different scenarios, such as moderate codeword lengths, high-order modulations, and burst error correction. Unfortunately, the complexity of NB-LDPC decoders is still too high for practical applications, especially for the check node (CN) processing, which limits the maximum achievable throughput. Although a great effort has been made in the recent literature to overcome this disadvantage, the proposed decoders are still not ready for high-speed implementations for high-order fields. In this paper, a simplified trellis min-max algorithm is proposed, where the CN messages are computed in a parallel way using only the most reliable information. The proposed CN algorithm is implemented using a horizontal layered schedule. The overall decoder architecture has been implemented in a 90-nm CMOS process for a (N = 837 and K = 726) NB-LDPC code over GF(32), achieving a throughput of 660 Mb/s at nine iterations based on postlayout results. This decoder increases hardware efficiency compared with the existing recent solutions for the same code.

In this brief, a method for compressing the messages between check nodes and variable nodes is proposed. This method is named compressed nonbinary message passing (CNBMP). CNBMP reduces the number of messages exchanged between one check node and the connected variable nodes from dc x q to 5 × q, and its application has a high impact on the performance of the decoder: the storage and routing areas are reduced and the throughput is increased. Unlike other methods, CNBMP does not introduce any approximation or modification in the information and the processed operations are exactly the same as those of the original decoders; hence, no performance degradation is introduced. To demonstrate its advantages, an architecture applying this CNBMP to the Trellis Min-Max algorithm was derived showing that most of the storage resources were also reduced from dc× q to 5 × q. This architecture was implemented for a (837 726) nonbinary low-density parity-check code using a 90-nm CMOS technology reaching a throughput of 981 Mb/s with an area of 10.67 mm2, which is 3.9 more efficient than the best solution found in the literature.

A simplified version of the enhanced serial generalized bit-flipping algorithm is proposed in this brief. This new algorithm reduces the quantity of information that is stored with a negligible performance loss of 0.05 dB compared with previous proposals. In addition, the algorithm allows us not only to save memory, but also to reduce the number of arithmetic resources needed. In addition, a new initialization of the algorithm avoids using techniques to control data growth without any performance degradation, reduces routing, increasing the maximum frequency achievable, and saves logic. The decoder derived from the simplified algorithm requires almost half the area of previous architectures, with a throughput of 716 Mbps on a 90-nm CMOS process for the (837, 723) nonbinary code over GF(32) at ten iterations.

A multiple-vote symbol-flipping (MV-SF) decoding algorithm for nonbinary low-density parity-check (NB-LDPC) codes is proposed in this paper. Our algorithm improves the generalized bit-flipping algorithm (GBFDA) by considering the multiplicity of the candidates at the check-node output, to perform a more accurate symbol-flipping decision at the variable node update. The MV-SF algorithm greatly improves the frame error rate performance of GBFDA and approaches the performance of the best state-of-the-art decoders [extended min-sum and min-max (Min–Max)] with lower complexity. For a$(N=837,K=723)$NB-LDPC code over GF(32), the decoder derived from the proposed algorithm can reach a throughput higher than 500 Mb/s and a coding gain of 0.44 dB compared with the most efficient GBFDA architecture with only twice the silicon area. Our architecture has 27% efficiency gain compared with the best Min–Max architecture found in the literature, with a performance loss of just 0.21 dB at frame error rate$10^{-4}$.

In this paper, a high-throughput interpolator architecture for soft-decision decoding of Reed-Solomon (RS) codes based on low-complexity chase (LCC) decoding is presented. We have formulated a modified form of the Nielson's interpolation algorithm, using some typical features of LCC decoding. The proposed algorithm works with a different scheduling, takes care of the limited growth of the polynomials, and shares the common interpolation points, for reducing the latency of interpolation. Based on the proposed modified Nielson's algorithm we have derived a low-latency architecture to reduce the overall latency of the whole LCC decoder. An efficiency of at least 39%, in terms of area-delay product, has been achieved by an LCC decoder, by using the proposed interpolator architecture, over the best of the previously reported architectures for an RS(255,239) code with eight test vectors. We have implemented the proposed interpolator in a Virtex-II FPGA device, which provides 914 Mb/s of throughput using 806 slices.