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K. S. Ramanatha

dblp:14/1103 · DBLP profile ↗
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5ranked-venue papers
4as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 4 first-authorComputer networks · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Routing and switching · 61% Transport protocols and congestion control · 30% Wireless networking · 9%
Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 100%

Topics — the 13 heaviest of 13, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Routing and switching
ad hoc network routing
0.112006
Mobile agents based framework for routing and congestion control in mobile ad hoc networks · CoNEXT 2006
Routing and switching › adaptive routing
congestion-aware routing
0.112006
Mobile agents based framework for routing and congestion control in mobile ad hoc networks · CoNEXT 2006
Transport protocols and congestion control
cross-layer congestion control
0.112006
Mobile agents based framework for routing and congestion control in mobile ad hoc networks · CoNEXT 2006
Wireless networking
mobile ad hoc networks
0.012006
Mobile agents based framework for routing and congestion control in mobile ad hoc networks · CoNEXT 2006
Electronic design automation
hardware verification and test
0.031988
Design of Crosspoint-Irredundant PLA's Using Minimal Number of Control Inputs · IEEE Trans. Computers 1988
A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays · IEEE Trans. Computers 1983
An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic Arrays · IEEE Trans. Computers 1983
Electronic design automation › hardware verification and test
design for testability
0.021988
Design of Crosspoint-Irredundant PLA's Using Minimal Number of Control Inputs · IEEE Trans. Computers 1988
A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays · IEEE Trans. Computers 1983
Electronic design automation
logic synthesis
0.011988
Design of Crosspoint-Irredundant PLA's Using Minimal Number of Control Inputs · IEEE Trans. Computers 1988
Electronic design automation › logic synthesis › programmable logic array
programmable logic array design
0.011988
Design of Crosspoint-Irredundant PLA's Using Minimal Number of Control Inputs · IEEE Trans. Computers 1988
Electronic design automation › hardware verification and test › VLSI testing
programmable logic array testing
0.021983
A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays · IEEE Trans. Computers 1983
An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic Arrays · IEEE Trans. Computers 1983
Electronic design automation › hardware verification and test
fault diagnosis
0.011983
An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic Arrays · IEEE Trans. Computers 1983
Approximation and online algorithms
set cover
0.011988
Design of Crosspoint-Irredundant PLA's Using Minimal Number of Control Inputs · IEEE Trans. Computers 1988
Electronic design automation › hardware test
fault localization
0.011983
An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic Arrays · IEEE Trans. Computers 1983
Electronic design automation › hardware verification and test
fault modeling
0.011983
A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays · IEEE Trans. Computers 1983

Methods — techniques the papers use, named apart from their topics

multi-agent system · 0.1cross-layer design · 0.1set covering formulation · 0.0cube representation · 0.0heuristic minimization · 0.0fault equivalence · 0.0control input insertion · 0.0adaptive testing · 0.0
YearPublicationVenuePosition
2006 Mobile agents based framework for routing and congestion control in mobile ad hoc networks
abstract
In this paper, we present a Mobile Agents based Framework for Routing and Congestion control in Mobile Ad Hoc Networks (MAFRC). The framework uses a cross-layer design approach where multiple intelligent agents present across the network protocol stack cooperate with each other and aid in finding efficient routes between source and destination pairs and also in controlling congestion in the network. The mobile agents at the network layer moving across the network collect the network connectivity information based on the congestion state provided by the static agent at the link layer. The congestion information brought by these mobile agents is further used in controlling congestion at the transport layer. This multi-agent cross-layer framework has been implemented and a preliminary performance evaluation has been carried out for the congestion aware routing and the cross-layer congestion control scheme in a simulation environment using NS-2 simulator. The results show better performance with respect to the performance parameters such as network throughput, end-to-end delay and routing overhead when compared to the network architecture which uses Ad Hoc On-demand Distance Vector (AODV) as a standard routing protocol and Tahoe TCP.
H. M. P. Shekhar, K. S. Ramanatha
CoNEXT2
1988 Design of Crosspoint-Irredundant PLA's Using Minimal Number of Control Inputs
abstract
The problem of determining a minimal number of control inputs for converting a programmable logic array (PLA) with undetectable faults to crosspoint-irredundant PLA for testing has been formulated as a nonstandard set covering problem. By representing subsets of sets as cubes, this problem has been reformulated as familiar problems. It is noted that this result has significance because a crosspoint-irredundant PLA can be converted to a completely testable PLA in a straightforward fashion, thus achieving very good fault coverage and easy testability.>
K. S. Ramanatha, Nripendra N. Biswas
IEEE Trans. Computers1
1983 An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic Arrays
abstract
An on-line algorithm is developed for the location of single cross point faults in a PLA (FPLA). The main feature of the algorithm is the determination of a fault set corresponding to the response obtained for a failed test. For the apparently small number of faults in this set, all other tests are generated and a fault table is formed. Subsequently, an adaptive procedure is used to diagnose the fault. Functional equivalence test is carried out to determine the actual fault class if the adaptive testing results in a set of faults with identical tests. The large amount of computation time and storage required in the determination, a priori, of all the fault equivalence classes or in the construction of a fault dictionary are not needed here. A brief study of functional equivalence among the cross point faults is also made.
K. S. Ramanatha, Nripendra N. Biswas
IEEE Trans. Computers1
1983 A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays
abstract
In this paper, the validity of single fault assumption in deriving diagnostic test sets is examined with respect to crosspoint faults in programmable logic arrays (PLA's). The control input procedure developed here can be used to convert PLA's having undetectable crosspoint faults to crosspoint-irredundant PLA's for testing purposes. All crosspoints will be testable in crosspoint-irredundant PLA's. The control inputs are used as extra variables during testing. They are maintained at logic 1 during normal operation. A useful heuristic for obtaining a near-minimal number of control inputs is suggested. Expressions for calculating bounds on the number of control inputs have also been obtained.
K. S. Ramanatha, Nripendra N. Biswas
IEEE Trans. Computers1
1982 A Design for Complete Testability of Programmable Logic Arrays
K. S. Ramanatha, Nripendra N. Biswas
ITC1