Recent advances in CMOS technology have enabled the implementation of high-performance and energy-efficient digital-intensive radio transceivers for fifth-generation (5G) and beyond (6G) wireless communication systems. Among the various transmitter architectures, the outphasing transmitter with constant-amplitude modulation, which allows the use of highly energy-efficient nonlinear power amplifiers, has garnered significant attention since it easily lends itself to a digital-intensive implementation, thus fully exploiting the benefits of scaled CMOS technologies. However, an outphasing transmitter with a delay-based phase modulator suffers from performance degradation due to mismatch-induced static nonlinearity. This paper presents a linearization algorithm that minimizes mismatch-induced static nonlinearity by reordering the unary-weighted delay elements. The effectiveness of this algorithm is demonstrated through simulations and its application to measured delay characteristics from a 22-nm FDSOI CMOS transmitter prototype in a system simulation. The proposed reordering algorithm results in a 7.94% points improvement from 10.63% in EVM and a 7.76dB enhancement from 25dB in ACLR for a 5G NR 64-QAM OFDM waveform with a 200MHz bandwidth.

This paper proposes a system-aware, fully programmatic and automated, process agnostic design methodology, which utilizes system-level simulations with the layout parasitics of the circuit under optimization included. The methodology is demonstrated with a design procedure for a comparator from specification to layout implementation in three analog-to-digital converter design examples with different specifications and applications without designer interaction. The procedure is shown to effectively converge towards performance achieved with ideal comparator in post-layout across two different semiconductor processes. While the methodology was demonstrated for design of comparators, the proposed system-aware methodology is generally applicable to any analog circuit, drastically reducing design time while providing a silicon ready circuit implementation purpose designed to the higher level system without human-in-the-loop.

Time-based analog-to-digital converters (ADCs) have recently gained attention because of their ability to reach high sample rates with good energy efficiency. The performance of most implementations is limited by the Voltage-to-Time Converter (VTC), hence necessitating thorough analysis on its performance. This paper derives expressions for the noise and linearity of a constant-slope VTC. The derived expressions provide an explicit link between the circuit parameters and VTC performance as well as offer insight on the available trade-offs. Based on the expressions, a general design methodology for constant-slope VTCs is proposed. The simulated verification with 28-nm CMOS shows good agreement with the presented analysis and with previously measured results, thereby corroborating the proposed design methodology. The presented design methodology allows the developed understanding between the VTC circuit parameters and performance metrics to be utilized in e.g. design exploration and algorithmic circuit optimization to find an optimal set of parameters for a given target specification.

The digital front-end of the communication transceivers envisioned for fifth-generation (5G) and beyond requires highly configurable high-performance digital signal processing (DSP) hardware operating at very high sampling rates to accommodate increasing signal bandwidths and support a range of modulation schemes and transmitter architectures. In this article, we present an efficient implementation of a highly configurable DSP hardware generator that can generate high-performance DSP hardware for multiple transmitter architectures including Cartesian, polar, outphasing, and multilevel outphasing modulators. The generated hardware unit, which consists of multistage multirate filters and other required DSP operations, runs at sample rates up to 4 GHz. The hardware supports an adjacent channel leakage ratio (ACLR) down to −48 dB and an error vector magnitude (EVM) of 0.78% with a 7-bit phase signal at a sampling rate of 4 GHz for multilevel outphasing modulation. Digital synthesis of the circuit in a 5-nm complimentary metal-oxide semiconductor (CMOS) process yields a core area consumption of 0.01 mm2 and an estimated power consumption of 37.2 mW for a 200-MHz bandwidth 5G new radio (NR) baseband (BB) signal.

Deep neural network (DNN) accelerators are increasingly integrated into sensing applications, such as wearables and sensor networks, to provide advanced in-sensor processing capabilities. Given wearables’ strict size and power requirements, minimizing the area and energy consumption of DNN accelerators is a critical concern. In that regard, computing DNN models in the time domain is a promising architecture, taking advantage of both technology scaling friendliness and efficiency. Yet, time-domain accelerators are typically not fully digital, limiting the full benefits of time-domain computation. In this work, we propose an all-digital time-domain accelerator with a small size and low energy consumption to target precision in-sensor processing like human activity recognition (HAR). The proposed accelerator features a simple and efficient architecture without dependencies on analog nonidealities such as leakage and charge errors. An eight-neuron layer (core computation layer) is implemented in 22-nm FD-SOI technology. The layer occupies$70 \times \,70\,\mu $m while supporting multibit inputs (8-bit) and weights (8-bit) with signed accumulation up to 18 bits. The power dissipation of the computation layer is 576$\mu $W at 0.72-V supply and 500-MHz clock frequency achieving an average area efficiency of 24.74 GOPS/mm2 (up to 544.22 GOPS/mm2), an average energy efficiency of 0.21 TOPS/W (up to 4.63 TOPS/W), and a normalized energy efficiency of 13.46 1b-TOPS/W (up to 296.30 1b-TOPS/W).

In this article, we comprehensively investigate the potential of the digital polar radio transmitter architecture for multi-user massive multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) downlink system. In terms of throughput performance, we derive a lower bound for the average sum-rate achievable with Gaussian signaling inputs and zero-forcing (ZF) precoding based on Bussgang decomposition. By diagonal approximation, we derive an approximate, yet accurate, model for the distortion caused by uniform polar quantization, which can be used to evaluate the corresponding sum-rate in closed form. To assess the power efficiency, we provide power consumption models with realistic parameters and values for the quantized polar and Cartesian transmitters, based on state-of-the-art integrated circuit (IC) designs and measurements. Extensive numerical results demonstrate that the proposed quantized polar transmitter can enable excellent performance in terms of average sum-rate, symbol error rate (SER), and out-of-band (OOB) emission level, compared to the Cartesian architecture. Furthermore, the power consumption comparisons show that the digital polar transmitter can save more than 36% in the energy consumption under 64-antenna setting in typical 5G enhanced mobile broadband use cases, thus making it highly appealing for future power-efficient massive MIMO transmitter implementations.

This article investigates the feasibility of combinerless multilevel outphasing transmitter as a potential architecture for large millimeter-wave (mmWave) phased arrays. We consider two distinct ways of distributing the component signals to the antennas and develop a model for the received signal at each radiated spatial direction from a phased array. Based on the received signal model, we derive expressions for the signal-to-distortion ratio as well as total power experienced at each spatial direction. Furthermore, antenna branch mismatches, overload distortion and quantization are considered, and an analytical model for the signal-to-distortion ratio at the intended receiver is derived. We additionally establish a model for comparing the achievable energy efficiency to those of the relevant reference methods. Extensive numerical experiments are carried out to verify the analytical works, and to assess the commonly used metrics of error vector magnitude (EVM) and total radiated power adjacent channel leakage ratio (TRP-ACLR). It is shown that the combinerless architecture is a valid option for mmWave phased arrays, demonstrating favorable EVM results and TRP-ACLR beyond the 28 dBc limit imposed by the 3GPP, even in the presence of the considered distortions. The conducted energy efficiency assessment shows that efficiency of the reference methods can be exceeded with sufficient amount of outphasing levels. The considered architecture is thus an interesting alternative for addressing the linearity vs. energy-efficiency challenge in mmWave phased-array systems.

Cyclic-coupled ring oscillators (CCRO), which consist of M ring oscillators each with N inverting stages, can be used in time-domain data converters to achieve sub-gate-delay resolution and improved phase noise performance compared to a single ring oscillator (RO). However, CCROs can oscillate in several different oscillation modes, where some modes contain overlapping phases. Such in-phase oscillations severely degrade the performance of a time-domain data converter by undermining the sub-gate-delay of the CCRO. This paper presents a design method to avoid the undesired in-phase oscillation modes, and thus achieve guaranteed maximal phase resolution regardless of the oscillation mode, by properly selecting the CCRO dimensions N and M. We show, both theoretically and with transistor-level simulations, that mode-agnostic maximum phase resolution can be ensured by selecting a prime M together with an N which is co-prime with M.

Time-interleaved analog-to-digital converters (TIADC) require channel matching in terms of offset, gain, and sampling clock skew to achieve best data conversion performance. Conventionally, correction of skew mismatch is realized with analog delay lines, making it challenging for high-speed ADC designs to achieve fine delay resolution over wide tuning range while maintaining low clock jitter. Digital skew correction allows greater flexibility than analog solutions, but is hindered by a significant hardware footprint. This paper demonstrates digital filter-based timing skew correction approach suitable for on-chip implementation. In a 10-bit 8-channel TI-ADC the proposed structure corrects mismatch magnitudes up to 0.12 sample period across 0.9 Nyquist band while requiring only 65% hardware of similar architectures of equivalent performance. The presented digital circuit uses reduced combinational paths and operates at a clock rate of single ADC channel, making it applicable for digitally-assisted high-speed TI-ADCs.

An integrated circuit that measures time intervals with high precision and accuracy has a wide range of applications including data conversion, ranging, and 3-D imaging. The resolution with which time intervals are quantized by a ring oscillator or delay line is limited by the minimum delay of an inverter in the technology. We propose the use of cyclic-coupled ring oscillators (CCROs) as a time-domain quantizer to achieve a combination of subgate-delay time resolution together with a short conversion time, thereby enabling data conversion with high resolution as well as high bandwidth. The resolution-power tradeoff in coupled oscillators is studied. Simulation indicates up to a factor-of-13 subgate-delay time resolution with 13 coupled oscillators. A real-time quantizing time-to-digital converter with coupled oscillators is designed for a time-domain analog-to-digital converter. Powered by a factor-of-8 subgate-delay time resolution of 1.6 ps obtained with nine coupled oscillators, and a sample time of 4 ns for 11-bit conversion, the converter delivers a 9.9-bit ENOB over a signal bandwidth of 125 MHz and an SFDR of 88 dB. Results demonstrate that CCROs is an attractive candidate as a high-precision high-linearity time-domain quantizer for data converters.

In this paper we propose two methods to boost the power supply rejection (PSR) of an output-capacitor-less low-dropout regulator (LDO). Our LDO is targeted for low-power system-on-chip applications, such as medical electronics, RFIDs, and IoT devices, where applied energy harvesting techniques induce large voltage ripple to supply line, thus requiring high PSR out of the LDO. The regulator utilizes a feed-forward path through the amplifier power supply rail to pass-transistor gate. Furthermore it includes a feed-forward amplifier to improve the frequency response and a feedback amplifier to stabilize the LDO, eliminating the need for an area consuming compensation capacitor. The proposed LDO is implemented in 28-nm CMOS technology. It supplies 700-mV output level with a current range of 0-5 mA and a 100-mV dropout voltage. The three amplifiers within our LDO consume only a total of 13 μA, thus regardless of increased complexity, high current efficiency of 99.74% is maintained. At the nominal load of 1 mA, low-frequency PSR reaches a value of -97 dB and at the high-frequency range of 1- 20 MHz PSR is boosted to remain below -20 dB and the region of 3-10 MHz below -30 dB.

A digital-friendly approach to implement injection-locked ring oscillators is proposed. We show that lock can be achieved by dynamically switching the delay of a delay element in a ring oscillator. A logic gate that generates the control signal for switching the delay, together with a one-bit controlled oscillator, inherently realizes a locking mechanism. Measurement results from a prototype circuit fabricated with a 28 nm CMOS process demonstrate the feasibility of the concept. The circuit with a measured lock range of 2.4-3.7 GHz occupies an area of 0.00043 mm2and consumes 0.18 mW power.

Full-Duplex (FD) transceiver architectures have recently gained increased attention due to their potential for doubling the theoretical spectral efficiency. One of the main challenges in FD transceivers is the self-interference (SI) from the local transmitter (TX). In this paper we present a novel analog SI cancellation technique through buried-gate signaling in the fully-depleted silicon-on-insulator (FD-SOI) process. The proposed technique attenuates the TX leakage in the receiver (RX) chain before gain is applied. This relaxes the dynamic range requirement of the later RX stages by the amount of attenuation offered by the buried-gate signaling. Further, in comparison to other published analog techniques, the proposed technique offers no penalty on RX noise figure. Measured results in a 28nm FD-SOI technology demonstrate 40-50dB of SI cancellation for TX leakage as high as -10dBm, and above 20dB for TX leakage of -5dBm, with no increase in the RX noise figure.

This paper describes implementation details of a digital-intensive phase modulator architecture that does not require a frequency synthesizer to cover a wide carrier frequency range. The phase modulator operation is based on toggling the output accurately during the sample period to generate the phase-modulated signal. The toggling instants within the sample period are calculated by DSP solvers that utilize linear interpolation. The interpolation effectively multiplies the phase signal sample rate by the modulator phase resolution, which enables wider signal bandwidth and a completely digital method of defining the transmitter carrier frequency. The phase modulator concept is verified by implementing it as a part of an outphasing transmitter in 28 nm CMOS. With a constant sample rate of 1.5 GHz and without any predistortion, the transmitter achieves better than -28 dBc ACLR with 100 MHz aggregated LTE downlink signal between 0.8-2.0 GHz carrier frequency.

This paper examines one source of spectral degradation in polar and multilevel outphasing transmitters. The degradation is caused by the amplitude signal appearing at the transmitter output as a baseband component, in addition to the desired RF signal. This baseband component contains sampling images and quantization noise across the spectrum. Thus, it adds noise at the signal band where it cannot be filtered and limits the achievable ACLR, particularly in wideband LTE and 5G systems. We analyze the origin of this phenomenon and related effects of system and signal parameters, and propose three design solutions for eliminating or alleviating the problem. Our analysis and simulations demonstrate that using a voltage-subtracting power combiner cancels the described degradation, potentially leading to significant improvement in spectral performance.

This paper presents a wideband blocker-tolerant Direct ΔΣ receiver (DDSR). Blockers are attenuated through selective input impedance matching and optimized gain design. The created impedance profile provides low receiver input impedance at blocker frequencies, while at desired frequencies, the impedance is boosted to matched condition through an up-converted positive feedback from the DDSR output. Receiver is evaluated in a 28nm fully-depleted silicon-on-insulator CMOS process with total power consumption of 25mW at 1V supply voltage. The receiver is designed for configurable operation from 0.7-2.7GHz, a baseband bandwidth of 10MHz, demonstrates a maximum noise figure of 6.2dB, and achieves a peak SNDR of 53dB with an out-of-band 1dB input compression point of -11.5dBm at 100MHz offset.

In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded class D. As a solution, we introduce a new on/off switching method based on logic gates utilizing two square wave voltages to produce either a similar square wave or a constant voltage. This method enables a higher level of integration by using low-voltage digital signals for on/off control, while eliminating the timing mismatch between output transistors caused by a level shifter. The simulated peak output power of the PA is 32.4 dBm, and its peak efficiency is 34.1%.

This paper presents the design of an integrated current-controlled oscillator (CCO) based readout front-end for neurochemical sensing applications. The readout front-end chip is implemented in 65 nm CMOS technology and occupies an area of 0.059 mm2. The proposed design supports an input current range of 1.2 μA (±600 nA) and can also be configured to support wider current range. The CCO-based structure utilized in this design results in noise averaging of the detected neurochemical input signal due to its inherent ΔΣfirst-order noise shaping and anti-alias filtering characteristics. Thus, the prototype chip achieves a current resolution of 100 pA and can detect dopamine concentrations as small as 10 μMol based on measured data from novel diamond-like carbon electrodes. In addition, the digital codes obtained from the readout front-end attain a signal-to-noise (SNR) of 82 dB and linearity limited effective-number-of-bits (ENOB) of 8 at full current range input, without employing any calibration or linearization techniques. The proposed read-out front-end consumes 33.7 μW of power in continuous operation.

In a 3-axis compass, the system tilt of the sensors needs to be compensated to calculate the heading of the compass correctly. A novel tilt compensation algorithm using the CORDIC algorithm is presented. Only five 2D-CORDIC operations are needed to ac quire the heading angle from three components of magnetic and acceleration data. This can be useful in ASIC and FPGA designs where the compass data needs to be compensated efficiently in terms of area and power. It is also possible to implement the correction algorithm in a micro-controller without a multiplier. The algorithm was tested in practice using a 3-axis magnetometer, a 3-axis accelerometer and FPGA.

In this paper, design and implementation of a multicarrier quadrature amplitude modulation (QAM) modulator for a wideband code division multiple access (WCDMA) base-station with a 14-bit on-chip D/A converter is described. The modulator is capable of modulating four carriers with four independent in phase (I) and quadrature (Q) data streams. The proposed modulator structure consists of an interpolation chain for data streams and four digital frequency synthesizer/modulators, which are based on a coordinate rotation digital computer (CORDIC) vector rotation algorithm. The interpolation chain consists of a root-raised cosine pulse shaping filter and three half-band filters for image filtering. The modulated carriers are combined to form a multicarrier WCDMA signal. The SINC-attenuation effect of a digital/analog (D/A) converter is canceled by an inverse-SINC predistortion filter. The multicarrier signal is converted to the analog domain with a 14-bit current steering D/A converter, which is integrated on the same silicon chip. The modulator is implemented with a 0.35-mum BiCMOS process with CMOS transistors only

A multicarrier QAM modulator for the wideband code division multiple access (WCDMA) basestation has been designed. The multicarrier modulator performs pulse shaping filtering for four baseband I and Q data streams. The filtered data is interpolated in three stages each interpolating with a factor of two. The modulation of four independent carriers is performed with the numerically controlled oscillators (NCO) which are based on the CORDIC vector rotation algorithm. The multi-carrier output is formed by summation of the modulated carriers. The SINC-attenuation effect of the D/A-converter is canceled by an inverse-SINC predistortion filter. The goal of the design process was to make the performance of the modulator limited by the 14-bit D/A-converter which can be considered as the state of the art available at IF frequencies.