Demo Data from EDBT 2026 / reviewers in the wild / expert
Gabriele Luculli
dblp:14/1231
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 2019
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Embedded and real-time systems · 76% Memory systems · 19% Parallel and multicore computing · 6% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 50% Program analysis · 50% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization
partial evaluation |
0.0 | 1 | 2002 | Value-sensitive automatic code specialization for embedded software · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Program analysis › dynamic analysis › profiling
value profiling |
0.0 | 1 | 2002 | Value-sensitive automatic code specialization for embedded software · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Embedded and real-time systems
program specialization |
0.0 | 1 | 2002 | Value-sensitive automatic code specialization for embedded software · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Memory systems
cache |
0.0 | 1 | 1997 | A cache-aware scheduling algorithm for embedded systems · RTSS 1997 |
Embedded and real-time systems › real-time scheduling › multicore scheduling
cache-aware scheduling |
0.0 | 1 | 1997 | A cache-aware scheduling algorithm for embedded systems · RTSS 1997 |
Embedded and real-time systems
real-time scheduling |
0.0 | 1 | 1997 | A cache-aware scheduling algorithm for embedded systems · RTSS 1997 |
Parallel and multicore computing › parallel scheduling
static scheduling |
0.0 | 1 | 1997 | A cache-aware scheduling algorithm for embedded systems · RTSS 1997 |
Methods — techniques the papers use, named apart from their topics
value profiling · 0.1partial evaluation · 0.1simulated annealing · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2019 | Methodology for risk management related to cyber-security of Unmanned Aircraft SystemsabstractNowadays, the market of Unmanned Aerial Systems (UAS) develops progressively with a lot of applications such as: infrastructure monitoring, law enforcement, environment research, goods transportation, etc. However, due to the lack of human observation, communication capacities, and protection, a UAS is an appropriate target for a criminal or a terrorist cyber attack. Therefore, risks related to the cyber-security need to be taken into account during the development of a UAS. This document presents a risk management methodology related to cyber-security. The expected result of the application of this methodology is a list of cyber-security requirements which guides the development of cyber-security countermeasures. Trung Duc Tran, Jean-Marc Thiriet, Nicolas Marchand, Amin El Mrabti, Gabriele Luculli |
ETFA | 5 |
| 2002 | Value-sensitive automatic code specialization for embedded softwareabstractThe objective of this work is to create a framework for the optimization of embedded software. We present algorithms and a tool flow to reduce the computational effort of programs, using value profiling and partial evaluation. Such a reduction translates into both energy savings and average-case performance improvement, while preserving a tolerable increase of worst case performance and code size. Our tool reduces the computational effort by specializing frequently executed procedures for the most common values of their parameters. The most effective specializations are automatically searched and identified, and the code is transformed through partial evaluation. Experimental results show that their technique improves both energy consumption and performance of the source code up to more than a factor of two, in average about 35% over the original program. Also, their automatic search engine greatly reduces code optimization time with respect to exhaustive search. Eui-Young Chung, Luca Benini, Giovanni De Micheli, Gabriele Luculli, Marco Carilli |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 4 |
| 1997 | A cache-aware scheduling algorithm for embedded systemsabstractThe paper presents a methodology for scheduling real time tasks in embedded systems where the task layout is known at design time and does not change at execution time (static systems) and where the cache miss costs are significant when compared to the normal execution time of the tasks. The scheduling model assumes a time driven dispatching of the application tasks which are ordered in a pre defined sequence. Building such a sequence in a way that is not only efficient but accounts for optimal cache sequencing is the aim of our method. The refinement of the schedule towards an optimal solution is done by simulated annealing techniques. The evaluation of the schedules is done by considering the effects of instruction caching when evaluating the computation time of the tasks. Gabriele Luculli, Marco Di Natale |
RTSS | 1 |