The advent of 5G networks has revolutionized wireless communication by providing enhanced data rates, ultra-low latency, and massive connectivity. However, these advancements demand highly efficient, flexible, and scalable hardware solutions to meet the rigorous requirements of next-generation communication systems. Field-Programmable Gate Arrays (FPGAs) have emerged as a pivotal technology in addressing these challenges, offering unparalleled reconfigurability, parallel processing capabilities, and hardware-level optimization for $5 G$ applications. This paper explores the integration of FPGAs in 5G infrastructure, focusing on their role in accelerating the security processing using the Authentication and Key Agreement (AKA) protocol. Additionally, the paper delves into design considerations, challenges, and future directions, highlighting FPGAs’ potential to drive innovation in 5G and beyond.

5G networks, and their future iterations like 6G, are vital for the EU's digital transformation and global competitiveness. Given their role in connecting EU systems and critical infrastructures, addressing security, privacy, and trust challenges is crucial. Securing these networks requires high-quality technical solutions and operational collaboration among stakeholders. SAND5G research project that is funded by Digital Europe Programme (DIGITAL) under the Cybersecurity and Trust (DIGITAL-ECCC-2022-CYBER-03) call, aims to deliver a risk assessment platform to help 5G stakeholders secure their systems, enable national authorities to oversee security measures, and align with European cybersecurity policies and proposed EU toolbox for 5G security.

The primary goal of this work is to introduce possible hardware solutions that can increase trust in cloud computing while maintaining data control in the hands of the data holder, in the framework of the collaborative environment provided by cloud computing. A software-based solution leads to possible anonymity or impersonation.

Phase aware speech processing has been recognized as important characteristic with significant contribution in denoising of voiced signals for the Audio of Things (AoT) implementations. Accurate representation of the time-frequency (TF) component for the extraction of the features, together with the complex operation of the deep neural networks (DNN) and the signal reconstruction are challenging tasks. Both can become more prominent when deployment is targeted for edge applications that hardware resources are causing limitations, while they are often exposed to conditions in low signal to noise ratio.In this paper, we present the hardware implementation for the inference of complex deep neural network in low cost and low resources embedded hardware platform for single channel speech enhancement. Using the proposed architecture, denoising of speech is achieved within the resources of a small size system on chip with field programmable gate array (SoC-FPGA), constructing a platform with heterogeneous processing capabilities.

In this paper, a very compact architecture the newest member of the SNOW family of stream ciphers, called SNOW-V, is presented. The proposed architecture has a 128-bit datapath and is pipelined in key areas in order to achieve the maximum possible frequency while using only a small number of hardware resources. The design was coded using the VERILOG hardware description language and the BASYS3 board (Artix 7 XC7A35T) was the target of the hardware implementation. The proposed implementation utilizes only 2109 FPGA LUTs and 1352 FFs and reaches a data throughput of 2.6 Gbps at 224 MHz clock frequency.

Hardware Trojan detection is a very serious issue for Integrated Circuit design and fabrication especially for those used in critical applications. The main target of this malicious hardware is to access and exploit the information stored and/or processed on an IC. Therefore, countermeasures must be designed for protection against HTs. In this direction many runtime and test-time monitoring approaches have been proposed. In run-time techniques, special monitoring sensors are used in order to detect local variations of the design characteristics, due to the presence of a HT. Most sensors are based on the classical ring oscillators that change their oscillation frequency when a HT is present. Recently two new types of oscillators without a combinatorial loop have been proposed, both different from the classical ring oscillators. In this paper a study and a statistical approach about the efficient use of the new oscillators as the main part of a HT detection technique, instead of the classical ring oscillator, are presented.

The present paper describes the design and implementation of a development board, designed in Digital Systems and Media Computing Laboratory of the Hellenic Open University which is very active in the field of digital systems design. The board hosts an MCU and an FPGA on the same PCB, cooperating with tight interconnection between them and supported by a set of basic on-board peripherals that cover some of the most essential educational examples in the field, minimizing the need for external devices. The design is geared i) towards ease of use in order to alleviate any initial setup stress by students or inexperienced designers and ii) towards low-cost fabrication in order to facilitate educational institutions who provide distance education to offer this board to every student for out-of-laboratory usage. The design process, consists of three main stages; the PCB design, the firmware development and the lastly the host computer software development. The architectural and design choices made for each stage are described fully later on the paper with each decision balancing between ease-of-use, cost and functionality, in the form of offered services. The board functions as a very low-cost laboratory educational platform for both low level HDL training as well as higher level MCU Firmware programming, supporting even more complex scenarios of FPGA softcore usage and programming or concurrent usage of FPGA and MCU in complete System-on-Chip (SoC) designs.

In this paper, a very compact architecture of the CLEFIA block cipher is presented. This architecture has a 128-bit plaintext/ciphertext and a 128-bit key and processes the data using a 4-bit datapath and therefore requires only a small number of hardware resources. The target of this architecture is ultra-low area devices for Internet of Things systems. The design was coded using the Verilog language and the BASYS3 board (Artix 7 XC7A35T) was used for the hardware implementation. The proposed implementation utilizes only 606 FPGA LUTs and 477 FFs and reaches a data throughput of 28 Mbps at 115 MHz clock frequency.

In this paper an FPGA Hardware Trojan (HT) detection approach based on multiple parameter analysis is proposed. In this direction, we apply a logic testing method, a run-time method and a side-channel analysis method. Logic testing and side-channel analysis methods are non-invasive while the run-time method is invasive in the sense that on-chip digital sensors are used to detect unexpected differentiations in the layout of the IC. The introduced methods do not rely on the presence of a "Golden chip" for detecting the HT. The proposed approach is implemented and evaluated on an actual FPGA board, providing practical results that validate our assumptions. To the best of our knowledge this is the first attempt for combining three different parameter analysis for HT detection in an of-the-shelf FPGA board.

Integrated circuits can be modified with malicious circuitries, like hardware trojans. The use of these circuitries, is either to leak confidential information, or disable security fence of a system, or even to the total destroy of the chip. In this work, several shift registers and a set of logic gates were used to implement key generators. A malicious hardware trojan circuit was added in the combinational circuit, to leak information that were generated. Only a few logical gates are needed to effectively trigger the malicious circuitry, in combination with a flip-flop. These additional gates, have to be included between the shift registers, to be triggered by certain signals, and not to leak in every clock cycle. Taking the advantage of the trigger effect, the malicious circuitry is not delaying the key generators. By implementing the above system, the ability of a hardware trojan to be stealthy under many circumstances, is proven. It is also introduced, from the low demand of logic gates, the little space that is obtained as the effect. It is also proven by the implementation, the very low cost of additional time, which is really needed to perform the leak. Merging those two advantages, the modified circuit that is resulted, is hard to be detected, by a number of applied methods. In particular, in this work a hardware trojan is implemented and added in a stream cipher hardware integration. It is proven, by the implementation results, that the spatial burden is about 2% while the temporal burden is about 3%.

This paper introduces an efficient technique for the detection of malicious hardware, based on thermal sensors. Each sensor consists of a Ring Oscillator with three inverters, a control multiplexer and a compact Residue Number System ring counter requiring only two FPGA slices. The sensors were placed in a 6×5 grid structure in equal distance from each other, in order to cover the whole area of the FPGA implementation causing a total overhead of only 1.9 %. To emulate a Hardware Trojan, a 64-bit Linear Feedback Shift Register was used. We demonstrate the proposed technique with an experimental system based on a XILINX Basys 3 board. The results from the experiments illustrate the efficiency of the proposed technique. According to our knowledge we are the first that we have used this kind of sensor for Hardware Trojan Detection.

The detection of malicious hardware logic (hardware Trojan) requires test patterns that succeed in exciting the malicious logic part. Testing of all possible input patterns is often prohibitively expensive. As an alternative, we explored previously the applicability of the combinatorial testing principles. In this paper, we turn our focus on the efficiency of this approach for triggering the hidden malicious logic. We present a series of experiments with Trojan designs of various activation patterns and lengths that target a cryptographic module performing AES cryptography. Our findings indicate that the available test suites succeed in triggering the malicious logic in all cases requiring only a very small number of test vectors. Thus, it is an efficient means for detecting malicious hardware logic.

A Transient Effect Ring Oscillator (TERO) is a special case of a Ring Oscillator (RO) design that exhibits increased sensitivity to intrinsic noise. It can serve as a basis for implementing a True Random Number Generator (TRNG) or a Physically Uncloneable Function (PUF). Also, as a digital sensor for detecting insertion of malicious hardware logic (Trojans) in digital circuits. Here, we explore the application of TERO for detecting hardware Trojans injected in FPGA implementations of the AES cryptographic algorithm. Experiments and comparisons are reported in terms of the frequency as a function of the TERO length. Our findings indicate that TERO-based digital sensors can be used to efficiently detect the presence of the Trojan.

A Ring Oscillator (RO) integrated in a design can be used for detecting insertion of malicious logic i.e., a hardware Trojan horse. Recently, the Transition Effect Ring Oscillator (TERO) was proposed as a means for implementing True Random Number Generators (TRNGs) and Physically Uncloneable Functions (PUFs). In this paper, we explore the timing sensitivity of TERO against RO, towards introducing TERO as an alternative means for detecting Trojans on FPGAs.

Contemporary hardware design shares many similarities with software development. The injection of malicious functionality (Trojans) in FPGA designs is a realistic threat. Established techniques for testing correctness do not cope well with Trojans, since Trojans are not captured in the system model. Furthermore, a well-designed Trojan activates under rare conditions and can escape detection during testing. Such conditions cannot be exhaustively searched, especially in the case of cryptographic core implementations with hundreds of inputs. In this paper, we explore the applicability of a prominent combinatorial strategy, namely combinatorial testing, for FPGA Trojan detection. We demonstrate that combinatorial testing provides the theoretical guarantees for exciting a Trojan of specific lengths by covering all input combinations. Our findings indicate that combinatorial testing constructs can improve the existing FPGA Trojan detection capabilities by reducing significantly the number of tests needed. Besides the foundations of our approach, we also report on first experiments that indicate its practical use.

Hardware Trojan horses are a realistic threat for both ASIC and FPGA systems. Ring Oscillators (ROs) can be used to detect the presence of malicious hardware functionality. The length of an RO is a significant parameter for detecting efficiently malicious logic (sensitivity) while maintaining a low space and power profile. We explore through simulation the effect of the RO length on detecting different classes of Trojan horses on an FPGA.

Skein is a hash function that reached the semifinals of the NIST competition for the selection of standard SHA-3. This paper describes the implementation of Skein-512 operating as simple hash function and as MAC function. The design was coded using VHDL language and for the hardware implementation, two XILINX FPGAs, Virtex-6 and Virtex-7 were used. The proposed implementation reaches a data throughput of 894 Mbps at 110 MHz clock frequency for Virtex-6 and a throughput of 975 Mbps at 120 MHz clock frequency for Virtex-7.

Keccak hash function has been submitted to SHA-3 competition and it belongs to the final five candidate functions. In this paper FPGA implementations of Keccak function are presented. The designs were coded using HDL language and for the hardware implementation, a XILINX Virtex-5 FPGA was used. Some of the proposed implementations use DSP48E blocks in order to accelerate the designs execution. So, comparisons between the proposed designs in terms of time performance and FPGA resources are given in order to examine the efficiency of the using DSP48E blocks. Also, comparisons with previous published works are provided.

In this paper a hardware implementation of ZUC stream cipher is presented. ZUC is a stream cipher that forms the heart of the 3GPP confidentiality algorithm 128-EEA3 and the 3GPP integrity algorithm 128-EIA3, offering reliable security services in Long Term Evolution networks (LTE). A detailed hardware implementation is presented in order to reach satisfactory performance results in LTE systems. The design was coded using VHDL language and for the hardware implementation, a XILINX Virtex-5 FPGA was used. Experimental results in terms of performance and hardware resources are presented.

Low power techniques in a FPGA implementation of the hash functions called JH and Fugue are presented in this paper. The JH hash function is under consideration for adoption as standard. Pipeline technique (with some variants) and the use of embedded RAM blocks are the techniques in order to reduce the power consumption. Power consumption reduction between 6.3% and 33 % was achieved for JH function and similar a power reduction between 1.7% and 13.3 % was achieved for Fugue by means of the proposed techniques compared with the implementation without any low power issue.

Low power techniques in a FPGA implementation of the hash function called Luffa are presented in this paper. This hash function is under consideration for adoption as standard. Two major gate level techniques are introduced in order to reduce the power consumption, namely the pipeline technique (with some variants) and the use of embedded RAM blocks instead of general purpose logic elements. Power consumption reduction from 1.2 to 8.7 times is achieved by means of the proposed techniques compared with the implementation without any low power issue.

An architecture and VLSI implementation of a new block cipher called Curupira is presented in this paper. This cipher is suitable for wireless sensors and RFID applications. Our 0.13 mum implementation requires resources of 9450 gate equivalences and is capable to encrypt a plaintext in 10 clock cycles. The cipher achieves a maximum throughput up to 2361 Mbps at 246 MHz for encrypting/decrypting. When clocked at 100 KHz a throughput of up to 960 Kbps is achieved and an average power of 0.04 mW is drawn.

With the rapid progress in information technology and an enormous amount of media appearing over Internet, e.g., text, audio, speech, music, image, and video, guaranteeing information security is becoming increasingly important. Several pivotal challenges include copyright protection, integrity verification, authentication, and access control etc. As a consequence, the subject of security protection in multimedia communication has attracted intensive research activities in academia, industry, and also government. Nowadays, multimedia data are used more and more widely in human's daily life. The typical applications include audio broadcasting, Digital TV, Mobile TV, etc., which are constructed on multimedia communication techniques. Associated with these applications, there are some security issues, e.g., multimedia content security, payment security and user privacy. To solve these issues, some means are required. During the past decades, various techniques have been reported for secure multimedia communication, including key management, multimedia encryption, authentication, digital watermarking, digital fingerprinting, access control, and digital rights management. Among them, multimedia encryption, authentication, digital watermarking, and digital fingerprinting aim to protect multimedia content's confidentiality, integrity, ownership, and traitor traceability. For example, digital fingerprinting embeds a unique customer code into multimedia content in order to produce a unique copy for the certain customer. Thus, the illegal redistribution of the media copy can be traced by detecting and comparing the embedded customer code. Some other techniques, e.g., key management, access control, and digital rights management, are able to protect payment security and user privacy. Taking access control for example, it permits only the authorized customer to access the multimedia content, while some other customers without payment often have limited access right. Additionally, in different networks such as Internet, 3G wireless, DVB-H, and p2p, different secure protocols and algorithms are required to provide the system security. For example, in DVB-H, the broad cast mode is used for data transmission, while in Internet-based services, the unicast or multicast mode is often used. Different from them, in p2p, the multi-hop transmission without the server is often used. When different networks are converged, the secure system with interactivity and interoperability is expected. All these topics are in active development. Furthermore, devices like digital cameras, mobile/video phones, graphics processing units, DVD player, etc. are expected to be equipped with such security mechanisms. In these situations, software solutions may not be adequate to provide high real-time performance. On the other hand, hardware assisted solutions are much better for easy integration with multimedia hardware, which has low power consumption, higher reliability/availability, and low cost. The aim of this special issue is to present a collection of high-quality research papers that report the latest research advances in secure transmission or distribution of multimedia content than on multimedia content protection. In this special issue, we selected 7 papers, which can demonstrate advanced works in this field. A detailed overview of the selected works is given below. The first paper, A Secure Virtual Point of Service for Purchasing Digital Media Content over 3G Wireless Networks, presents the secure virtual point of service (SVPOS) for secure multimedia content transactions and payments. The proposed solutions based on 3rd generation partnership project (3GPP) generic authentication architecture (GAA) and standard charging and billing protocols (e.g., Parlay-X) guarantees some desirable privacy and security properties, including privacy of subscribers, protection of 3G operator and merchant, and interaction security. The scheme is suitable for cell phone based merchant purchase in 3G networks. The second paper, Realising Time-limitation for Cryptographic Keys in Secure Multimedia Distribution, reports a promising transmission infrastructure and key construction scheme for future multimedia delivery. In particular, the scheme is transmitting the encoded layers on separate streams which will be secured using SRTP. This allows fast adaptation by just dropping layers if necessary. The session keys used for SRTP are time-limited and hierarchically dependent such that only one key is necessary for the client to decrypt all desired layers. Although the prerequisites for choosing the initial values of the time-limited keys are fairly high, this structure implies less administration effort. The third paper, Integrating Fingerprint with Cryptosystem Internet-Based Live Pay-TV System, proposes a new architecture to protect contents from unauthorized viewing and illegal redistribution for an internet-based live pay-TV system. Code embedding is considered in order to enhance the resistance against collusion of fingerprinted video. The paper has demonstrated that the proposed scheme can provide higher security and better trade-off between image and video encryption and fingerprinting imperceptibility than existing works. The paper also indicates the ongoing implementation of the pay broadcasting system based on the proposed architecture. The fourth paper, User Plane Security Alternatives in the 3G Evolved Multimedia Broadcast Multicast Service (e-MBMS), proposes a secure multicast overlay (SMO) approach and describe how to implement based on a proof-of-concept test-bed over public domain Linux routers. The paper demonstrates that SMO is able to achieve a low risk of denial of service attacks, significant advantages in terms of impact on the architecture and on device requirements, and high security association management and key management. The fifth paper, Step-wise Inter-frame Correlation-based Steganalysis System for Video Streams, reports a collusion scheme among video frames to find out whether secret data is hidden in frames or not. The effect of local motion interfering detection precision is studied. The local motion and message embedded in video frame is treated as a bimodal noise. To reliably detect the existence of the embedded message, block-wise correlation-based steganalysis scheme is proposed to reduce the local motion interfering effect. The video steganalysis process is divided into two stages. In the first stage, suspicious video frames will be recognized by decision module employing features extracted with a light-weight collusion scheme. In the second stage, suspicious frames will be analyzed critically by the present powerful image steganalysis schemes. In addition, the determine principle is also studied to reduce the false positive rate in first stage. Experimental results have been presented to show the performance of the proposed strategy. The sixth paper, AuthoCast - a Mobility-compliant Protocol Framework for Multicast Sender Authentication, introduces a protocol framework for authenticating multicast sources and securing their mobility handovers. Using a self-consistent, one-way authentication based on cryptographically generated addresses, a common design is derived to jointly comply with the mobile any source and source specific multicast protocols that are currently proposed. This light-weight scheme smoothly extends the unicast enhanced route optimization for mobile IPv6 and adds only little overhead to multicast packets and protocol operations. The seventh paper, Early Security Key Exchange for Encryption in Mobile IPv6 Handoff, proposes an early security key exchange for encryption in Mobile IPv6 handoff in order to reduce the security latency. In the approach, two issues are addressed in dealing with the latency within the encryption technology during the handover. First, the study extends the early binding update method to deal with the long security exchange negotiation time for the Mobile IPv6 handoff. Secondly, the study adopts the security access gateway (SAG) to solve the limited computing and memory in the mobile node. In conclusion, this issue of Security and Communications Networks offers a ground-breaking view into the recent advances in secure multimedia communications. This issue offers both academic and industry appeal- the former as a basis toward future research directions, and the latter toward viable commercial applications. Finally, we would like to express our gratitude to the Editor-in-Chief, Dr. Hsiao-Hwa Chen for his advice, patience, and encouragements since the beginning until the final stage. Special thanks go to Michelle in Wiley during the production. We thank all anonymous reviewers who spent much of their precious time reviewing all the papers. Their timely reviews and comments greatly helped us select the best papers in this special issue. We also thank all authors who have submitted their papers for consideration for this issue. We hope you will enjoy reading the great selection of papers in this issue.

Abstract Universal mobile telecommunication system (UMTS) has specified security mechanisms with extra features compared to the security mechanisms of previous mobile communication systems (GSM, DECT). A hardware implementation of the UMTS security mechanism is presented in this paper. The proposed VLSI system supports the Authentication and Key Agreement procedure (AKA), the data confidentiality procedure, and the integrity protection procedure. The AKA procedure is based on RIJNDAEL Block Cipher. An efficient RIJNDAEL architecture is proposed in order to minimize the usage of hardware resources. The proposed implementation performs the AKA procedure within 76 µs comparing with the 500 ms that UMTS specifies. The data confidentiality and the integrity protection is based on KASUMI Block Cipher. The proposed KASUMI architecture reduces the hardware resources and power consumption. It uses feedback logic and positive‐negative edge‐triggered pipeline in order to make the critical path shorter, without increasing the execution latency. The S‐BOXes that are used from RIJNDAEL and KASUMI block ciphers have been implemented with combinational logic as well as with ROM blocks. Copyright © 2006 John Wiley & Sons, Ltd.