MOTIVATION: Developing a robust and performant data analysis workflow that integrates all necessary components whilst still being able to scale over multiple compute nodes is a challenging task. We introduce a generic method based on the microservice architecture, where software tools are encapsulated as Docker containers that can be connected into scientific workflows and executed using the Kubernetes container orchestrator. RESULTS: We developed a Virtual Research Environment (VRE) which facilitates rapid integration of new tools and developing scalable and interoperable workflows for performing metabolomics data analysis. The environment can be launched on-demand on cloud resources and desktop computers. IT-expertise requirements on the user side are kept to a minimum, and workflows can be re-used effortlessly by any novice user. We validate our method in the field of metabolomics on two mass spectrometry, one nuclear magnetic resonance spectroscopy and one fluxomics study. We showed that the method scales dynamically with increasing availability of computational resources. We demonstrated that the method facilitates interoperability using integration of the major software suites resulting in a turn-key workflow encompassing all steps for mass-spectrometry-based metabolomics including preprocessing, statistics and identification. Microservices is a generic methodology that can serve any scientific discipline and opens up for new types of large-scale integrative science. AVAILABILITY AND IMPLEMENTATION: The PhenoMeNal consortium maintains a web portal (https://portal.phenomenal-h2020.eu) providing a GUI for launching the Virtual Research Environment. The GitHub repository https://github.com/phnmnl/ hosts the source code of all projects. SUPPLEMENTARY INFORMATION: Supplementary data are available at Bioinformatics online.

SUMMARY: AliView is an alignment viewer and editor designed to meet the requirements of next-generation sequencing era phylogenetic datasets. AliView handles alignments of unlimited size in the formats most commonly used, i.e. FASTA, Phylip, Nexus, Clustal and MSF. The intuitive graphical interface makes it easy to inspect, sort, delete, merge and realign sequences as part of the manual filtering process of large datasets. AliView also works as an easy-to-use alignment editor for small as well as large datasets. AVAILABILITY AND IMPLEMENTATION: AliView is released as open-source software under the GNU General Public License, version 3.0 (GPLv3), and is available at GitHub (www.github.com/AliView). The program is cross-platform and extensively tested on Linux, Mac OS X and Windows systems. Downloads and help are available at http://ormbunkar.se/aliview CONTACT: [email protected] SUPPLEMENTARY INFORMATION: Supplementary data are available at Bioinformatics online.

The increasing test-data volumes needed for the testing of system-on-chip (SOC) integrated circuits lead to long test-application times and high tester memory requirements. Efficient test planning and test-data compression are therefore needed. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. This implies that for a given set of compression schemes, there is no compression scheme that is the optimal with respect to test time reduction and test-data compression at all TAM widths. We therefore propose a technique where we integrate core wrapper design, test architecture design and test scheduling with test-data compression technique selection for each core in order to minimize the SOC test-application time and the test-data volume. Experimental results for several SOCs crafted from industrial cores demonstrate that the proposed method leads to significant reduction in test-data volume and test time.

The ever-increasing test data volume for core-based system-on-chip (SOC) integrated circuits is resulting in high test times and excessive tester memory requirements. To reduce both test time and test data volume, we propose a technique for test-architecture optimization and test scheduling that is based on core-level expansion of compressed test patterns. For each wrapped embedded core and its decompressor, we show that the test time does not decrease monotonically with the width of test access mechanism (TAM) at the decompressor input. We optimize the wrapper and decompressor designs for each core, as well as the TAM architecture and the test schedule at the SOC level. Experimental results for SOCs crafted from several industrial cores demonstrate that the proposed method leads to significant reduction in test data volume and test time, especially when compared to a method that does not rely on core-level decompression of patterns.

The increasing test-data volumes needed for the testing of system-on-chip (SOC) lead to long test times and high memory requirements. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. Therefore, we propose a technique where compression-technique selection is integrated with core wrapper design, test architecture design, and test scheduling to minimize the SOC test time and the test-data volume.

The increasing test data volume needed to test core-based system-on-chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requirements. TAT and ATE memory requirement can be reduced by test architecture design, test scheduling, sharing the same tests among several cores, and test data compression. We propose, in contrast to previous work that addresses one or few of the problems, an integrated framework with heuristics for sharing and compression and a constraint logic programming technique for architecture design and test scheduling that minimizes the TAT without violating a given ATE memory constraint. The significance of our approach is demonstrated by experiments with ITC '02 benchmark designs

Due to the increasing test data volume needed to test corebased System-on-Chip, several test scheduling techniques minimizing the test application time have been proposed. In contrast to approaches where a fixed test set for each core is assumed, we explore the possibility to use overlapping test patterns from the tests in the system. The overlapping tests serves as alternatives to the original dedicated test for the cores and, if selected, they are transported to the cores in a broadcasted manner so that several cores are tested concurrently. We have made use of a Constraint Logic Programming technique to select suitable tests for each core in the system and schedule the selected tests such that the test application time is minimized while designer-specified hardware constraints are satisfied. The experimental results indicate that we can on average reduce the test application time with 23%.

The increasing amount of test data needed to test SOC (system-on-chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the chip. Having a powerful TAM shorten the test time, but it costs large silicon area to implement it. Hence, it is important to have an efficient TAM with minimal required hardware overhead. We propose a technique that makes use of the existing bus structure with additional buffers inserted at each core to allow test application to the cores and test data transportation over the bus to be performed asynchronously. The non-synchronization of test data transportation and test application makes it possible to perform concurrent testing of cores while test data is transported in a sequence. We have implemented a Tabu search based technique to optimize our test architecture, and the experimental results indicate that it produces high quality results at low computational cost.

We present a monolithic technique for simultaneous mode and polarization control in oxide-confined VCSELs using a locally etched sub-wavelength surface grating. A single-fundamental mode emission with an SMSR>30 dB and an OPSR~20 dB is achieved over the entire operational current range, with a maximum output power of 4.1 mW

Learning is a highly individual process.Some prefer learning by reading the course material, others learn best by listening to a lecture, while some like to learn in a trial-and-error way by themselves in a laboratory assignment. A good learning scheme is individual. A scheme that is good for some persons might not at all be good scheme for someone else. It is important to understand your own personal way to learn, but also when organizing a course individual learning alternatives should be acknowledged.Examination in a course can be seen as a test occasion or as a learning occasion. Traditionally, examination has been an occasion where knowledge is tested. Written exams can be used to test the theory and laboratory work to test practical aspects of the course material. For laboratory work the distinction between learning and test of learning is somewhat unclear.The learning and the test of learning are mixed. However, in general,examination can be seen as an occasion to learn and/or to test knowledge.We have, in a Computer Architecture course, taken the view that (1) learning is an individual process, and (2) that examination is a learning occasion. The consequence of our view (1) + (2) is basically that examination should be individual, or student-oriented. Alternatives to traditional examination is also supported when taking gender, cultural, and age perspectives. We therefore developed two examination tracks where the students in the beginning of the course decided what track to follow. Common for both tracks is that credits are given that can be counted for in the written exam. The students, individually or in pair, define their own laboratory task related to a course topic such as cache-memories or pipelines, solve the task and present the results in front of the class. Each student designs individually a multiple-choice pre-exam question (specifying what it tests, the question and correct answer). A student friend corrects the question and might improve it if needed. The teaching assistant selects questions for the multiple-choice pre-exam. Each student also creates individually one exam question, which a student friend corrects and if needed improves. Each part (lab presentation, creation and evaluation of pre-exam questions, pre-exam, and creation and evaluation of exam question) is given credits that are included in the written exam.