Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Cheng-Chih Yang

dblp:14/1390 · DBLP profile ↗
← Back
5ranked-venue papers
1as first author
0since 2021 · last 2010
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Graphics, computer vision, multimedia, augmented reality and games · 2 · 1 first-authorHuman-computer interaction and ubiquitous computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › clock network synthesis
adjustable delay buffer allocation
0.112010
Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Electronic design automation › physical design › clock network synthesis
clock skew optimization
0.112010
Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Electronic design automation › physical design › clock network synthesis
clock tree synthesis
0.112010
Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Electronic design automation
physical design
0.112010
Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010

Methods — techniques the papers use, named apart from their topics

linear-time optimal assignment · 0.1heuristic buffer placement · 0.1
YearPublicationVenuePosition
2010 Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers
abstract
In synchronous circuit designs, clock skew is difficult to minimize because a single physical layout of a clock tree must satisfy multiple constraints in a complicated power mode environment where certain modules may operate with different voltages. In this paper, we use adjustable delay buffers (ADB) whose delays can be tuned or adjusted to minimize clock skew under different power modes. Assuming that the positions of$k$ADBs are already determined, we first propose a linear-time optimal algorithm which assigns the values of ADBs so that the skew is optimal among all possible ADB assignments with a possibility of latency penalty. Then, we propose a modified optimal algorithm without latency penalty. We also propose an efficient heuristic to determine good positions for ADBs. Our results show significant improvement when compared to cases without ADBs.
Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang 0001, Yeong-Jar Chang
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
2009 Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs
abstract
In synchronous circuit designs, clock skew is difficult to minimize because a single physical layout of a clock tree must satisfy multiple constraints in a complicated power mode environment where certain modules may operate with different voltages. In this paper, we use Adjustable Delay Buffers (ADB) whose delays can be tuned or adjusted to minimize clock skew under different power modes. Assuming that the positions of k ADBs are already determined, we propose a linear-time optimal algorithm which assigns the values of ADBs so that the skew is optimal among all possible ADB assignments. We also propose an efficient heuristic to determine good positions for ADBs. Our results show significant improvement when compared to cases without ADBs. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids — Optimization General Terms: Algorithms, Reliability
Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang 0001, Yeong-Jar Chang
ICCAD3
2007 Efficient and Effective Video Copy Detection Based on Spatiotemporal Analysis
abstract
In this paper, a novel method is presented to detect video copies for a given video query. These copies and the query have identical or near-duplicate content, which might differ in their spatiotemporal structures slightly. To address both the efficient and effective issues, we conduct the bag-of words model for video feature representation, and apply a coarse-to-fine matching scheme to analyze the video spatiotemporal structure. The proposed method can deal with various kinds of video transformations, such as cropping, zooming, speed change, and subsequence insertion/deletion, which are not well addressed in existing methods. Besides, two indexing methods are employed to speed up the matching process. Experimental results show that the proposed method can behave in an efficient and effective manner.
Chih-Yi Chiu, Cheng-Chih Yang, Chu-Song Chen
ISM2
2007 A NOR Emulation Strategy over NAND Flash Memory
abstract
This work is motivated by a strong market demand in the replacement of NOR flash memory with NAND flash memory to cut down the cost in many embedded-system designs, such as mobile phones. Different from LRU-related caching or buffering studies, we are interested in prediction-based prefetching based on given execution traces of application executions. An implementation strategy is proposed in the storage of the prefetching information with limited SRAM and run-time overheads. An efficient prediction procedure is presented based on information extracted from application executions to reduce the performance gap between NAND flash memory and NOR flash memory in reads. With the behavior of a target application extracted from a set of collected traces, we show that data access to NOR flash memory can be responded effectively over the proposed implementation.
Jian-Hong Lin, Yuan-Hao Chang 0001, Jen-Wei Hsieh, Tei-Wei Kuo, Cheng-Chih Yang
RTCSA5
2005 Visualization for High-Dimensional Data: VisHD
abstract
This paper presents a visualization tool, VisHD, that can visualize the spatial distribution of vector points in high dimensional feature space. It is important to handle high dimensional information in many areas of computer science. VisHD provides several methods for dimension reduction in order to map the data from high dimensional space to low dimensional one. Next, this system builds intuitive visualization for observing the characteristics of the data set, whether these data are pre-defined labels or not. In addition, some useful functions have been implemented to facilitate the information visualization. This paper, finally, gives some experiments and discussions for showing the abilities of VisHD for visualizing high-dimensional data.
Cheng-Chih Yang, Cheng-Chieh Chiang, Yi-Ping Hung, Greg C. Lee
IV1