Analog-to-digital converters based on voltage-controlled oscillators (VCO-ADCs) can be employed in the readout circuit of a Microelectromechanical system (MEMS) microphone, as an alternative to classical voltage-encoding architectures. In the presence of a high sound pressure, larger than the microphone Acoustic Overload Point (AOP), or after a mechanical shock is applied to the sensor, undesired audible artifacts generated by spurious tones falling into the audio band can appear, impairing the shock recovery capability of the microphone. This paper presents a spurious-free VCO-ADC suitable for audio applications. The proposed idle-tone mitigation mechanism is based on introducing a sampling inaccuracy in the form of clock jitter modulation. Measurements of an ASIC implemented in 130 nm CMOS technology show the effectiveness of the proposed solution.

This paper presents a Companding Silicon Microphone System achieving 70dB SNR (A-weighted) measured at 1Pa - 1kHz input signal (-34dBFS digital output level). The combination of inverter-based techniques and a DAC-on-demand approach in the Delta-Sigma ADC helps to reduce the power consumption of the complete product to only 460μW. Robustness against MEMS asymmetries and programmable Acoustic Overload Point (AOP) are included. Developed in a CMOS 130nm technology, the ASIC has an approximated area of 1.1mm2(including all auxiliary circuits).

In this manuscript, we propose a time-domain, mostly digital band-pass filter architecture for audio signal feature extraction. The filter is composed of a single voltagecontrolled-oscillator (VCO) as signal encoder and monostables generating digital pulses at the edges of the pulse frequency modulated VCO output. The band-pass filtering phenomena are observed when we combine these digital pulses with different lengths, and its functionality is proved by the behavioral simulations performed with a circuit proposal built in MATLAB/Simulink. Compared to other state-of-the-art solutions, our filter architecture can take the benefit from advancement of digital technology nodes and design tools thanks to its mostly digital implementation. Moreover, the band-pass filter possesses friendly programmability, whose center frequency can be easily tuned by modifying the digital pulse length, and the single VCO encoder promises an easy calibration circuit. Finally, a recurrent neural network is trained and tested based on the features extracted from this architecture, the excellent speech/non-speech hitting rate shows the feasibility of our band-pass filters for voice activity tasks.

A voice activity detector architecture based on an analog feature extractor and a mixed signal classification stage is proposed for ultra-low power activity. The feature extraction stage is composed of a set of analog band-pass filters and frame energy estimators. The classification stage has a fully connected first layer built with ultra-low power consumption ring oscillators, followed by gated recurrent unit layers. The ring oscillator based layer consumes nWs according to transient simulations performed in a low power 65 nm CMOS technology. Additionally it features the ability to perform the analog-to-digital conversion required to handle subsequent GRU layers, as well as the possibility of computing a non-linear function like sigmoid seizing the intrinsic non-linearity of the ring oscillator. Training and testing operations are made proving competitive classification performance between a baseline model and our proposed architecture. In light of this, proper features for deployment on power-restricted edge-computing applications are shown.

Digital sensors contain reconfigurable Sigma-Delta modulators that support different working modes. Depending on the timing of reconfiguration, high amplitude transients may appear at the sensor output. This article analyzes the transient response of discrete time Sigma-Delta modulators to find the optimal reconfiguration moment. It is shown that the transient is optimal when the first state variable of the loop filter is zero at the reprogramming instant. The optimal time is predicted with a pulse frequency modulator model. Finally, a set of general equations are given to predict the transient sequence for any modulator order and topology.

Single-bit ΣΔ modulators are prone to exhibit idle tones in stable operation. In audio applications the human hear can perceive this tonal behavior degrading the quality of the application. Classical solutions to overcome this problem are the use of dithering signals or chaotic modulators. In this work we compare these methods with the addition of a Fractional Delay FIR filter. The proposed technique is analyzed in terms of NTF modification and complexity, as well as the effectiveness of the technique in reducing high frequency idle tones; the impact on the modulator performance is also studied.

Capacitive or resistive sensors can be included in the feedback network of an oscillator to implement a data acquisition system. A higher sampling rate, compared with standard oversampled converters, is required to maintain a sufficient SNR in this case. In this paper, we propose an architecture based on a LC-CMOS oscillator and a digital interface that can be completely integrated on chip and satisfies low clock specifications of standard microphone capacitive interfaces. The complete system outputs one-bit bitstream at 15.53MHz and achieves SNR of 55.38dB for -26dBfs input tone.

Clock jitter is an important source of error in highspeed current-steering D/A converters. A technique to compensate these errors is introduced. Simulations show a significant reduction to clock jitter sensitivity for the example of a sigma delta DAC with an analog bandwidth (ABW) of 30 MHz clocked at 360 MHz