Neuromorphic computing is a novel computational paradigm that draws inspiration from the structure and function of the human brain. Spiking Neural Networks (SNNs) are a promising approach for implementing energy-efficient Artificial Neural Networks (ANNs) in embedded systems. In this article, we present ModNEF, an open-source, neuromorphic digital hardware architecture designed for Field Programmable Gate Arrays (FPGAs). ModNEF is based on a modular architecture, where independent modules communicate via point-to-point connections to emulate SNNs. Our architecture offers two neuron models based on the Leaky Integrate and Fire (LIF) model, with a different emulation strategy. The modular nature of ModNEF allows researchers to extend the architecture by developing new modules to emulate different types of neurons or implement online learning rules. ModNEF is a clock-driven emulator, meaning that the neuron state is updated at regular intervals, even in the absence of input data. We evaluated the performance of the emulator using the MNIST and NMNIST datasets, with offline, full-precision training.

Hyperparameter optimization of spiking neural networks (SNNs) is a difficult task which has not yet been deeply investigated in the literature. In this work, we designed a scalable constrained Bayesian based optimization algorithm that prevents sampling in non-spiking areas of an efficient high dimensional search space. These search spaces contain infeasible solutions that output no or only a few spikes during the training or testing phases, we call such a mode a "silent network". Finding them is difficult, as many hyperparameters are highly correlated to the architecture and to the dataset. We leverage silent networks by designing a spike-based early stopping criterion to accelerate the optimization process of SNNs trained by Spike Timing Dependent Plasticity (STDP) and surrogate gradient. We parallelized the optimization algorithm asynchronously, and ran large-scale experiments on heterogeneous multi-GPU Petascale architecture. Results show that by considering silent networks, we can design more flexible high-dimensional search spaces while maintaining a good efficacy. The optimization algorithm was able to focus on networks with high performances by preventing costly and worthless computation of silent networks.

This paper advocates for the integration of environmental aspects in computing curricula, with a focus on higher education. We created knowledge-based curriculum specifications in order to help teachers who wish to add knowledge foundation on computing impacts. This document lists topics and references that can be integrated into curricula. We implemented it in several higher education institutions. This paper reports on our experience and feedback. We also discuss recommendations to overcome obstacles that, from our experience, are often faced when modifying computing curricula to integrate environmental challenges.

Summary Neuromorphic architectures are one of the most promising architectures to reduce the energy consumption of tomorrow's computers. These architectures are inspired by the behavior of the brain at a fairly precise level and consist of artificial spiking neural networks. To optimize the implementation of these architectures, we propose in this article a novel progressive network compression and reinforcement technique. This technique consists of two functions: progressive pruning and dynamic synaptic weight reinforcement, which we apply after each training batch. The proposed approach delivers a highly compressed network (up to 80% of compression rate) while preserving the network performance when tested with MNIST.

Bio-inspired computing architectures enable ultra-low power consumption and massive parallelism using neuromorphic computing, which is apt to implement Spiking Neural Networks (SNN). Such architectures are particularly suitable for energy-constrained applications. A deeper understanding of Spiking Neural Networks (SNN) behavior during training is needed to improve these architectures. This paper presents VS2N, a web-based tool for interactive visualization and analysis of SNN activity over time. This simulator-independent tool offers a way to examine, analyze and validate different hypotheses about SNN activity. We present available analysis modules and use-cases of the tool as an example.

Spiking neural networks (SNNs) are good candidates to produce ultra-energy-efficient hardware. However, the performance of these models is currently behind traditional methods. Introducing multi-layered SNNs is a promising way to reduce this gap. We propose in this paper a new threshold adaptation system which uses a timestamp objective at which neurons should fire. We show that our method leads to state-of-the-art classification rates on the MNIST dataset (98.60%) and the Faces/Motorbikes dataset (99.46%) with an unsupervised SNN followed by a linear SVM. We also investigate the sparsity level of the network by testing different inhibition policies and STDP rules.

Many task models have been proposed to express and analyze the behavior of real-time applications at different levels of precision. Most of them target sequential applications with no support for parallelism. The digraph task model is one of the most general ones, as it allows modeling arbitrary directed graphs (digraphs) for sequential job releases. In this paper, we extend the digraph task model to support intra-task parallelism. For the proposed parallel multi-mode digraph model, we derive sufficient schedulability tests and a dichotomic search to improve the test pessimism for a set of n tasks onto a heterogeneous single-ISA multi-core platform. To reduce the computational complexity of the schedulability test, we also propose heuristics for (i) partitioning parallel digraph tasks onto the heterogeneous cores, and (ii) assigning core operating frequencies to reduce the overall energy consumption, while meeting real-time constraints. The effectiveness of the proposed approach is validated with an exhaustive set of simulations.

Image recognition tasks require multi-layer networks to achieve good performance on complex data. However, building multi-layer spiking neural networks (SNN) still remains unreachable. One cause is that the learning mechanism of these models decreases the spiking activity throughout the layers. We propose three mechanisms to solve this issue without impacting the performance of the network: target frequency threshold adaptation, which forces neurons to reach a desired frequency, binary coding, which improves the performance of the network at high levels of activity, and mirrored STDP, which improves the convergence of the training. Experiments on single layer networks show that these mechanisms preserve both the recognition rate and the level of spiking activity.

Model-Driven Engineering (MDE) encourages the use of graphical modeling tools, which facilitate the development process from modeling to coding. Such tools can be designed using the MDE approach into metamodeling environments called metaCASE tools. It turned out that current metaCASE tools still require, in most cases, manual programming to build full tool support for the modeling language, especially for users' native methodologies and representational elements and suffer from gaps in terms of reusability. In this context, we propose MID, a set of metamodels supporting the specification of modeling editors by means of reusable components and explain how representational metamodeling is carried out with it.

Due to the definition of fUML (Foundational Subset for Executable UML Models) along with its action language Alf (Action Language for fUML), UML (Unified Modeling Language) allows the production of executable models on which early verification and validation activities can be conducted. Despite this effort of standardization and the large use of UML in industry, developers still hand tune the code generated from models to correct, enhance or optimize it. This results in a gap between the model and the generated code. Manual code tuning except from being error prone can invalidate all the analysis and validations already done in the model. To avoid the code hand tuning drawbacks and, since UML is becoming an executable language, we propose a new Model Based Development (MBD) approach that skips the code generation step by compiling directly UML models. The biggest challenge for this approach - tackled in this paper is to propose a model compiler that is more efficient than a code compiler for UML models. Our model compiler performs optimizations that code compilers are unable to perform resulting in a more compact assembly code.

Model-Based Development (MBD) provides an additional level of abstraction, the model, which lets engineers focus on the business aspect of the developed system. MBD permits automatic treatments of these models with dedicated tools like synthesis of system's application by automatic code generation. Real-Time and Embedded Systems (RTES) are often constrained by their environment and/or the resources they own in terms of memory, energy consumption with respect to performance requirements. Hence, an important problem to deal with in RTES development is linked to the optimization of their software part. Although automatic code generation and the use of optimizing compilers bring some answers to application optimization issue, we will show in this paper that optimization results may be enhanced by adding a new level of optimizations in the modeling process. Our arguments are illustrated with examples of the Unified Modeling Language (UML) state machines diagrams which are widely used for control aspect modeling of RTES. The well-known Gnu Compiler Collection (GCC) is used for this study. The paper concludes on a proposal of two step optimization approach that allows reusing as they are, existing compiler optimizations.

This paper addresses the problem of code optimization for Real-Time and Embedded Systems (RTES). Such systems are designed using Model-Based Development (MBD)approach that consists of performing three major steps: building models, generating code from them and compiling the generated code. Actually, during the code generation, an important part of the modeling language semantics which could be useful for optimization is lost, thus, making impossible some optimizations achievement. This paper shows how adding a new level of optimization at the model level results in a more compact code. It also discusses the impact of the code generation on optimization: whether this step promotes or prevents optimizations. We conclude on a proposal of a new MBD approach containing only steps that advance optimization: modeling and compiling steps.

This paper presents an approach for the modeling and formalvalidation of high-performance systems. The approach relies on the repetitive model of computation used to express the parallelism of such systems within the Gaspard framework, which is dedicated to the codesign of high-performance system-on-chip. The system descriptions obtained with this model are then projected on the synchronous model of computation. The result of this projectionconsists of an equational model that allows one to formally analyze clock synchronizability issues so as to guarantee the reliable deployment of systems on platforms.