Military microsensors are networked distributed embedded systems composed of a processor, a radio, and sensors used for personnel or vehicle detection. They are most often found in minefield replacement and perimeter security applications where size, weight, power, and cost requirements are quite challenging. In this paper, we discuss the different system design approaches used in microsensor systems and introduce a modular, scalable, power-aware microsensor architecture intended span the entire dynamic range required of these systems. We describe a reference implementation of this concept and results from field experiments.

We introduce a power-aware microsensor architecture supporting a wide operational power range (from10 W). The platform consists of a family of modules that follow a common set of design principles. Each module includes a local power microcontroller, power switches, and isolation switches to enable independent power-down control of modules and module subsystems. Processing resources are scaled appropriately on each module for their role in the collective system. Hard real-time functions are migrated to the sensor and radio modules for improved power efficiency. The optional Linux-based processor module supports high duty cycling and advanced sleep modes. Our reference hardware implementation is described in detail in this paper. Seven different modules have been developed. We utilize an acoustic vehicle tracking application to demonstrate how the architecture operates and report on results from field tests on tracked and wheeled vehicles.

In the past, government agencies played pivotal roles in the development of new technologies. For example, Internet is an outgrowth of the ARPAnet project sponsored by the Defense Advanced Research Projects Agency (DARPA) of the United States government. Recently, consortia of private industries, often in cooperation with government agencies, have entered into this picture. As a consequence, researchers in academia have shifted their attentions much more towards real-world applications. In the panel discussion, we first compare the traditional roles of funding agencies in the USA, EU, and Asia. We then focus on the new trends in this funding business in each of the three regions. We will examine why and how such shifts have been made and discuss the roles of funding agencies to be played in the coming years. In particular, we will attempt to search for future roles and new forms/ways of the funding agencies from the viewpoint of economic development driven by technology advancement.

The Adaptive Computing Systems (ACS) program was initiated by Defense Advanced Research Projects Agency (DARPA) of the United States in 1996. With the advent of FPGAs, has emerged a new class of computing systems that contain configurable hardware. This session begins by a presentation by the first ACS program manager of its motivation, original goals, and objectives. It is then followed by presentations of four specific projects under the ACS program. Future activities surrounding the ACS community will be discussed at the end.

Adaptive computing systems use FPGAs for custom hardware acceleration in high performance and real-time applications. Unlike single purpose dedicated hardware approaches, the reusable nature of the technology introduces system design tradeoffs that must balance processing density, memory, and I/O bandwidth, not to mention more subtle issues such as ease of programming, debugging, and physical integration into real-world systems. This paper describes results from the DARPA-funded SLAAC project, which developed three generations of adaptive computing systems for a diverse set of challenging signal processing applications.

No abstract available.

One of the fundamental challenges for modern high-performance network interfaces is the processing capabilities required to process packets at high speeds. Simply transmitting or receiving data at gigabit speeds fully utilizes the CPU on a standard workstation. Any processing that must be done to the data, whether at the application layer or the network layer, decreases the achievable throughput. This paper presents an architecture for offloading a significant portion of the network, processing from the host CPU onto the network interface. A prototype, called the GRIP (Gigabit Rate IPSec) card, has been constructed based on an FPGA coupled with a commodity Gigabit Ethernet MAC. Experimental results based on the prototype are presented and analyzed. In addition, a second generation design is presented in the context of lessons learned from the prototype.

Many applications require the use of multiple, loosely-coupled adaptive computing boards as part of a larger computing system. Two such application classes are embedded systems in which multiple boards are required to physically interface to different sensors/actuators and applications whose computational demands require multiple boards. In addition to the adaptive computing boards, the computing systems for these application classes typically include general-purpose microprocessors and high-speed networks. The development environment for applications on these large computing systems is not unified. Typically, a developer uses VHDL simulation and synthesis tools to program the FPGAs on the adaptive computing boards. External control for the board, such as downloading new configurations or setting clock speeds, is provided through a vendor-specific API. This API is typically accessed in a C host program that the developer must write in a high-level language environment. Finally, the developer is responsible for writing the networking code that allows interaction between the separate adaptive computing boards and general-purpose microprocessors. No tools are available for either debugging or performance monitoring in this agglomerated system. Development on these systems is time-consuming and platform-specific. A standard ACS API is proposed to provide a developer with a single API for the control of a distributed system of adaptive computing boards, including the interconnection network.

The mission of the Systems-Level Applications of Adaptive Computing (SLAAC) project is to design and implement a distributed adaptive computing systems architecture. This systems-level focus of SLAAC resulted from the realization that scalability and portability are the two main obstructions preventing innovative Adaptive Computing Systems (ACS) research from being directly useful in deployed real-time environments. Scalability is an issue in that many real-world applications are larger than the modern PCI-based FPGA accelerator. Transitioning from a small proof of concept demonstration to large real-world application is often overlooked in ACS research. Portability has both a hardware and software aspect. Physical form-factor and operating system issues can limit the utility ACS research done in the lab with desktop PCs unless there is a development path to more traditional real-time environments. The SLAAC project seeks to remedy these issues of scalability and portability in ACS systems.

Software tools, including debuggers and performance monitors, have been developed independently for specific adaptive systems. Consequently, a user has to learn a new set of tools when switching to a different architecture. Although at the level closest to the hardware the runtime system is necessarily different for specific systems, much of the runtime system software functionality is common across systems and could be standardized. In this paper, we propose the SLAAC (system level applications of adaptive computing) reference architecture to help address some of the issues in the adaptive computing community.

Supervising student teams who worked with expert practitioners to build prototype expert systems has yielded insights into the frustrations and rewards of the early stages of knowledge engineering. This paper presents these insights to the expert systems community, particularly those beginning their first project or entering a wholly new application area. We focus on example based rule induction shells without imprecision. While such tools are generally too limited for implementing a finished, deliverable expert system, they are useful for “breaking the ice” with a quick, inexpensive demonstration system while acquiring the vital first elements of the eventual expert knowledge base.