In recent years, memristor emulators have been utilized in a wide range of applications including neuromorphic computing, security, analog signal processing, and other related fields. This article introduces a novel electronically tunable dual flux controlled floating memristor emulator employing single Current Controlled Differential Difference Current Conveyor (CCDDCC), a MOS capacitor, and one PMOS transistor. The core of the suggested emulator features an electronically tunable CCDDCC-based feedback circuit. The proposed circuit avoids passive components, diodes, and analog multiplier circuits. The suggested memristor has the ability to tune the area of the pinch hysteresis loop without altering the input frequency, input voltage, MOS capacitance, and active component. The circuit operates effectively within a 300 MHz frequency range and demonstrates a well-defined pinched hysteresis loop. Its performance is evaluated using 180 nm TSMC parameters, with a compact layout area of 758.12 μm². Additionally, the robustness of the circuit is thoroughly assessed through analyses of temperature variations, supply voltage fluctuations, transistor size variations, and process corner simulations.

A new active building block namely, subtractor connected first-generation current conveyor (S-CCI) is introduced in this paper. A simulated floating inductor (SFI) and two new quadrature oscillators (QOs) employing only one S-CCI are introduced as application examples. The introduced SFI employs two resistors with a single matching requirement and a grounded capacitor. Each of the introduced QOs has one grounded resistor, one floating resistor, and two grounded capacitors without any matching problems. Non-ideality analyses are performed. Furthermore, a third-order filter application is given. A layout of the S-CCI in$0.18 \mu \text{m}$technology occupying the area of about$71\,\,\mu \text{m}\,\,\times 44\,\,\mu \text{m}$is given. Also, numerous post layout simulations based on the SPICE program are accomplished. Moreover, several experiments are realized to confirm the theory.

Fractional-order differentiation and integration stages are essential building blocks for performing signal processing using fractional-order calculus. One important characteristic of fractional-order differentiators/integrators is the circuit complexity of the integer-order topologies required for approximating such stages. The already introduced schemes suffer from this obstacle, making the derived structures power demanding. A simple structure, constructed from 21 MOS transistors and 3 dc current sources, which is capable of approximating fractional-order differentiators and integrators is presented in this paper. Other attractive benefits of the proposed scheme are the electronic tuning capability as well as the capability for implementation in monolithic form. The evaluation of its behavior is performed using Cadence and the Design Kit provided by the Austrian Mikro Systems (AMS) 0.35μm CMOS process.

In this paper, a new realization of a fully-differential (F-D) first-order all-pass filter (APF) operating in current mode (CM) is presented. In the proposed F-D CM APF a single adjustable current amplifier (ACA) and two current followers (CFs) with non-unity gain are used as active building blocks. Considering the input intrinsic resistance of CFs as useful active filter parameter, the proposed filter employs only a floating capacitor as external passive component. The pole frequency of the proposed resistorless circuit can be tuned via mutual change of input intrinsic resistance of CFs while the filter pass-band gain by means of gain of ACA. The theoretical results are verified by SPICE simulations, where TSMC 0.18 μm level-7 SCN018 CMOS process parameters were used.

Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.

In this letter, complementary metal-oxide-semiconductor (CMOS) implementation of a neural network (NN) classifier with several output levels and a different architecture is given. The proposed circuit operates in current mode and can classify several types of data. The classifier circuit is designed using a current-voltage converter, an inverter followed by a NOR gate and a voltage-current output stage. Using a 0.35-m TSMC technology parameters, SPICE simulation results for a classifier with two inputs are included to verify the expected results.