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Mamoru Umemura

dblp:14/2408 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1985
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1Databases, data management, data science and information retrieval · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%
Databases, data mining, and information retrieval
1 paper
Database system architecture and tuning · 100%

Topics — the 1 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › instruction set architecture › instruction set style
stack architecture		 0.011985
Design of a High-speed Prolog Machine (HPM) · ISCA 1985

Methods — techniques the papers use, named apart from their topics

compiler-oriented architecture · 0.0
YearPublicationVenuePosition
1985 Design of a High-speed Prolog Machine (HPM)
abstract
This paper describes a High-speed Prolog Machine (HIM) architecture and its hardware structure, which are developed as a product of Fifth Generation Computer System (FGCS} project in Japan.HIM realizes high performance and provides a practical programming environment.A major HIM feature is a large memory capacity and specialized hardware for unification and stack operations.HIM has a compiler-oriented architecture with high-level stack-control instructions.Furthermore, the HIM architecture provides side-effect operations, nonlocal-exit control and multiprocess support primitives, which are effective to develop system programs.The performance is estimated at 280 KLIPS (Kilo Logical Inferences Per Second) in executing a deterministic "concatenate" Prolog program.The HIM processor is implemented with high-speed CCML {Current Mode Logic) chips and with I00 nanosecond machine cycle.
Ryosei Nakazaki, Akihiko Konagaya, Shinichi Habata, Hideo Shimazu, Mamoru Umemura, Masahiro Yamamoto, Minoru Yokota, Takashi Chikayama
 ISCA5
1977 A Conceptual Design of a Generalized Database Subsystem
Katsuya Hakozaki, Takenori Makino, Masayuki Mizuma, Mamoru Umemura, Shigeki Hiyoshi
 VLDB4