Motivation: The increasing amount of next-generation sequencing data poses a fundamental challenge on large scale genomic analytics. Existing tools use different distributed computational platforms to scale-out bioinformatics workloads. However, the scalability of these tools is not efficient. Moreover, they have heavy run time overheads when pre-processing large amounts of data. To address these limitations, we have developed Sparkhit: a distributed bioinformatics framework built on top of the Apache Spark platform. Results: Sparkhit integrates a variety of analytical methods. It is implemented in the Spark extended MapReduce model. It runs 92-157 times faster than MetaSpark on metagenomic fragment recruitment and 18-32 times faster than Crossbow on data pre-processing. We analyzed 100 terabytes of data across four genomic projects in the cloud in 21 h, which includes the run times of cluster deployment and data downloading. Furthermore, our application on the entire Human Microbiome Project shotgun sequencing data was completed in 2 h, presenting an approach to easily associate large amounts of public datasets with reference data. Availability and implementation: Sparkhit is freely available at: https://rhinempi.github.io/sparkhit/. Contact: [email protected]. Supplementary information: Supplementary data are available at Bioinformatics online.

Digital refocusing has a tradeoff between complexity and quality when using sparsely sampled light fields for low-storage applications. In this paper, we propose a fast physically correct refocusing algorithm to address this issue in a twofold way. First, view interpolation is adopted to provide photorealistic quality at infocus-defocus hybrid boundaries. Regarding its conventional high complexity, we devised a fast line-scan method specifically for refocusing, and its 1D kernel can be 30× faster than the benchmark View Synthesis Reference Software (VSRS)-1D-Fast. Second, we propose a block-based multi-rate processing flow for accelerating purely infocused or defocused regions, and a further 3- 34× speedup can be achieved for high-resolution images. All candidate blocks of variable sizes can interpolate different numbers of rendered views and perform refocusing in different subsampled layers. To avoid visible aliasing and block artifacts, we determine these parameters and the simulated aperture filter through a localized filter response analysis using defocus blur statistics. The final quadtree block partitions are then optimized in terms of computation time. Extensive experimental results are provided to show superior refocusing quality and fast computation speed. In particular, the run time is comparable with the conventional single-image blurring, which causes serious boundary artifacts.

This paper presents a self-sustainable landslide surveillance system that detects hazardous water content level in soils and provides real-time landslide warnings to residents, without requiring wired electricity transmission. A self-powered soil water content sensor was applied as the trigger of alert event. It solves the energy supply problem by an environmental interrupt mechanism, which wakes up the sensor and communication circuits in a sensing node only when the water content in monitored soils exceeds a certain threshold, and thus completely eliminates the need for an ALS node to periodically wake up, sense and communicate. By tightly integrating energy harvesting, environment sensing and circuit wake-up, it may well be the most energy-efficient landslide surveillance system designed to monitor water content in soils in the world.

View-interpolation-based refocusing achieves realistic quality for sparse light fields but requires lots of computation. In this paper, we aim to reduce the computation load while maintaining the superior refocusing quality. The idea is to interpolate only few views for infocused regions and to perform refocusing on downsampled pixels for defocused area. This is achieved b y a proposed block-based refocusing algorithm which consists of multi-level refocusing mode decision and timing-based bloc k merging. For each variable-size block, the former chooses the fastest downsampling mode given that the distortion is negligible based on a localized filter response analysis. Then, the latter determines the fastest quadtree block partition by minimizing the timing cost which is accurately estimated for each block. Experimental results show that a 10x speedup on average is achieved for realistic refocusing. Also, the computation time becomes comparable to the conventional fast depth-dependent blurring which has serious boundary artifacts.

This paper addresses the testing and characterization of interposer wires in a 2.5-D stacked integrated circuit, which is essential for yield learning and silicon debug. The proposed method provides a number of distinctive features beyond previous works on interposer wire testing. First, we target not only catastrophic types of faults (such as stuck-at faults or hard bridging faults), but also parametric types of faults (including both resistive open faults and resistive bridging faults between interposer wires). Second, our method can also be used to characterize the propagation delay across each fault-free interposer wire.

Testing the quality of the interposer wires in a 2.5-D stacked IC can avoid the penalty arising from bonding known-good dies to a defective interposer. However, an interposer is particularly hard to test alone due to the lack of a device layer. This paper addresses this problem by proposing amid-bond test method - in which the interposer is tested after each die is attached to the substrate. We borrow the technique of pre-bond test method for the TSV and enhance it by a length-normalization scheme to cope with interposer wires of diverse wire lengths. Simulations show that this mid-bond test method can catch a high percentage of open faults before subsequent dies are attached.

Delay testing and characterization of interposer wires in a 2.5-D stacked IC is essential for yield learning and silicon debug. This paper addresses this problem by proposing a data analysis flow for perturbation-based oscillation test method to cope with the various wire-lengths of the interposer wires. With the proposed method, one can not only detect small delay faults but also characterize the delay across each fault-free interposer wire.

Testing the quality of prebond through-silicon vias (TSV) is a vital part of the Known-Good-Die test that is often necessary to retain a high compound yield for 3-D stacked integrated circuits. In this paper, we present a versatile prebond TSV test method applicable before wafer thinning when the deep end of the TSV is inaccessible as buried in the still-thick wafer. Technical merits include: 1) the ability to handle both the resistive open fault and the leakage fault in the same test structure; 2) a capability that allows an user to have a better measure of the severity of the fault; and 3) an all-digital and easy to implement design-for-testability circuit.

Leakage tests have been a challenge for through-silicon vias (TSVs) in a 3-D IC. Most existing methods are still inadequate in terms of the range of testable leakage currents. In this paper, we borrow the wisdom of the IO-pin leakage test while enhancing it with two features. First, we make it more suitable for a TSV, which has a much smaller capacitance than an IO pin. Second, we support a wide range of leakage test (e.g., from 0.125 μA to 16 μA), and thereby allowing for flexible test threshold setting and leakage characterization. To achieve this goal, we present two sets of techniques-1) wait-time generation by programmable delay line, and 2) wait-time propagation with a self-timed timing control scheme to overcome the timing skew problem due to signal routing. We demonstrate that the entire scheme can be done in only logic gates, making it easy to integrate into the common design flow.

Fault management is an essential function of the network management to secure continuous and efficient operations of a network system. We initiate the fault management study for the adjustable pre-allocation wavelength division multi-access system (AP-WDMA). The subjects investigated include fault detection, fault location, and fault tolerant design. Based on the fault probability consideration for each station, two models are presented. One treats each station as a whole unit and the other further divides each station into 5 parts. For both models, the fault detection and fault location are performed in a two-pass operation. Finally, a fault-tolerant design for the AP-WDMA is proposed. A 2-stage reconfiguration algorithm is also provided in this study.

This paper presents a new and efficient strategy of pseudorandom pattern generation (PRPG) for IC testing. It uses a general programmable LFSR (P-LFSR) to offer multiple-seed and multiple-polynomial PRPG. The deterministic pattern set generated by an ATPG tool or supplied by the designers is used to guide the generation of pseudorandom patterns. A novel application of the Gauss-elimination procedure is proposed to find the seeds as well as the polynomials. With an intelligent heuristic to further utilize the essential faults, this approach becomes very efficient, even for the random pattern resistant (RPR) circuits. Experiments are conducted on the ISCAS-85 benchmarks and the full scan version of the ISCAS-89 benchmarks. For all benchmark circuits, complete fault coverage is achieved with good balance on the hardware overhead and the test lengths as compared to other schemes.

One major drawback of the LFSR-based BIST is its low fault coverage. To obtain the complete fault coverage, multiple seeds and multiple polynomials are usually required. One way to find the seeds and polynomials for the LFSR was utilizing the Gauss-elimination procedure. In this approach, the test patterns which are generated by LFSR are modeled as a set of multivariable linear equations. It is created from a given deterministic test set. The corresponding seed and polynomial are then obtained from the solution of this equations set. However, given the original deterministic test set without don't cares, it were not acceptable on the random pattern resistant circuits. In this paper, we allow the test patterns to have don't care values. With an intelligent heuristic of further utilizing the essential faults, this approach becomes much more efficient even for the random pattern resistant circuits. The experimental results on the ISCAS-85 and the ISCAS-89 benchmarks show that a significant improvement can be obtained both on the hardware overhead and the test length.

Most existing behavioral synthesis systems concentrate on area and performance optimization, while ignoring other design qualities such as testability. In this paper/sup /spl Dagger//, we present three algorithms for register, module, and interconnection allocation of behavioral synthesis respectively to improve testability in data path allocation without assuming any specific test strategy. By using primary input/output registers effectively, the proposed algorithms produce RTL designs with better testability, while incur low or even no hardware overhead. Four benchmarks are synthesized using the proposed approaches and the results are compared with the best results of similar works in the literature. It shows that our approaches give both higher fault coverage and lower hardware overhead.