Demo Data from EDBT 2026 / reviewers in the wild / expert
Wei-Yi Yang
dblp:14/3071
· DBLP profile ↗
2ranked-venue papers
1as first author
2since 2021 · last 2023
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 46% Memory systems · 46% Energy-efficient computing · 7% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.7 | 1 | 2023 | An Energy-Efficient Inference Engine for a Configurable ReRAM-Based Neural Network Accelerator · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Memory systems
processing-in-memory |
0.7 | 1 | 2023 | An Energy-Efficient Inference Engine for a Configurable ReRAM-Based Neural Network Accelerator · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › DNN accelerator
ReRAM-based DNN accelerator |
0.7 | 1 | 2023 | An Energy-Efficient Inference Engine for a Configurable ReRAM-Based Neural Network Accelerator · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Memory systems › processing-in-memory
ReRAM crossbar |
0.7 | 1 | 2023 | An Energy-Efficient Inference Engine for a Configurable ReRAM-Based Neural Network Accelerator · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Energy-efficient computing
power management |
0.2 | 1 | 2023 | An Energy-Efficient Inference Engine for a Configurable ReRAM-Based Neural Network Accelerator · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023 |
Methods — techniques the papers use, named apart from their topics
dynamic reference voltage scaling · 0.7analog-to-digital converter design · 0.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | An Energy-Efficient Inference Engine for a Configurable ReRAM-Based Neural Network AcceleratorabstractResistive random-access memory (ReRAM) offers a potential solution to accelerate the inference of deep neural networks by performing processing-in-memory. However, the peripheral circuits of ReRAM crossbars used to perform arithmetic operations consume significant amounts of power. Based on a power consumption analysis of the ReRAM crossbar circuits, we propose using the dynamic reference voltage scalable analog-to-digital circuits (ADCs) to conduct the dot product operation to enable the reconfigurability of the ReRAM-based neural network (NN) accelerator while maintaining accuracy. We propose a configurable ReRAM-based NN accelerator to provide various degrees of computing granularity with different levels of power consumption, creating a tradeoff between performance and power consumption in the given NN. Next, we develop an energy-efficient inference engine for the configurable ReRAM-based NN accelerator, EIF, to assign the operation unit (OU) size to perform vector-matrix multiplication (VMM) based on the data dependence of the NN. Our evaluation shows that the proposed EIF provided an energy savings of up to 36% over the state-of-the-art ReRAM-based accelerator while maintaining performance without resource duplication. Yang-Lin Zheng, Wei-Yi Yang, Ya-Shu Chen, Ding-Hung Han |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2022 | A Lazy Engine for High-utilization and Energy-efficient ReRAM-based Neural Network AcceleratorabstractResistive random-access memory (ReRAM) has been explored to be a promising solution to accelerate the inference of deep neural networks at the embedded systems by performing computations in memory. To reduce the latency of the neural network, all the pre-trained weights are pre-programmed in ReRAM cells as device resistance for the inference phase. However, the system utilization is decreased by the data dependency of the deployed neural networks and results in low energy efficiency. In this work, we propose a Lazy Engine for providing high utilization and energy-efficient ReRAM-based accelerators. Instead of avoiding idle time by applying ReRAM crossbar duplication, Lazy Engine delays the start time of the vector-matrix multiplication operations, with run-time programming overhead consideration, to reclaim idle time for energy efficiency while improving resource utilization. The experimental results show that Lazy Engine achieves up to 77% and 96% improvement in resource utilization and energy saving compared to state-of-the-art ReRAM-based accelerators. Wei-Yi Yang, Ya-Shu Chen, Jin-Wen Xiao |
INDIN | 1 |