In this paper we have presented a hardware implementation of 32-bit Fault-tolerant ALU (Arithmetic and Logic Unit) which is compared with the current techniques, Residue code, Triple Modular Redundancy (TMR) with single voting and TMR with triplicated voter that are widely used in space application to mitigate the upsets, in terms of area penalty. We consider BCH (Bose, Chaudhuri, and Hocquenghem) codec (encoder, decoder) using the prototyping FPGA (Field Programmable Gate Array). The new implementation of ALU employing BCH code on Spartan-3 FPGA has been provided. The results show that our fault tolerant method has the lowest hardware overhead and it can correct any 5-bit error in any position of 32-bit input registers of ALU.

To address the problem of accurate timing characterization, this paper proposes a method that fully exploits mode dependency. It is based on the premise that circuit delays are determined largely by a set of control inputs for which the number of useful combinations, i.e., modes, is small for most practical circuits. We take the mode-dependent characterization approach further and enhance it so that the delays of the I/O paths between the control inputs and outputs are calculated more accurately. We prove that, with a careful choice of propagation conditions, our method can generate timing models with very tight path delays that are guaranteed to give correct results. Experimental results using real-life circuits show that cir-cuit delays can vary significantly among different modes for both control and data input delays, and capturing this variation can have a significant impact on the overall system timing.

In deep submicrometer integrated circuit design, there is a growing need to quickly and accurately characterize the timing of large circuit blocks. Accurate timing characterization requires making available as much timing information as possible at each step of the design process. Conventional fast characterization methods typically employ topological analysis, which can be inaccurate because of its inability to eliminate false paths. To address this problem, a new method for creating accurate timing models of circuit blocks by making efficient use of their functionality is introduced. The proposed mode-dependent characterization (ModeChar) method is based on calculating a distinct timing model for each mode of circuit operation and reflects the way practical circuits function. ModeChar produces a mode-dependent timing model that contains delay information for a given set of circuit modes. It is shown that circuit delays are never underestimated by the mode-dependent models. The concept of mode dependency is taken further by extending it to sequential circuits. Given a sequential circuit, a compact set of constraints is derived for each circuit mode that captures all the timing constraints that must be satisfied for correct operation of the circuit. Experimental results are presented that demonstrate the effectiveness of ModeChar in eliminating many false paths that would otherwise result in performance penalties. In addition, our experiments indicate that delays can vary considerably among circuit modes, making conventional topological analysis overly pessimistic. To make the mode-dependent models more compact, an efficient algorithm far coalescing delay information is also introduced.

A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays using delay models can result in reduced accuracy. Instead, the proposed method calculates delays through numerical integration using an embedded circuit simulator. It takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst case delay for each gate. Similar repeating transistor configurations of gates in the circuit are automatically identified and a novel interpolation based caching scheme quickly computes gate delays from the delays of similar gates. A tight object code level integration with a commercial high speed transistor level circuit simulator allows efficient invocation of the simulation.

A method that characterizes the timing of Intellectual Property (ZP) blocks while taking into account IP functionality is presented.IP blocks are assumed to have multiple modes of operation specified by the user.For each mode, our method calculates IO path delays and timing constraints to generate a timing model.The method thus captures the mode-dependent variation in IP delays which, according to our experiments, can be as high as 90%.The special manner in which delay calculation is performed guarantees that IP delays are never underestimated.The resulting timing models are also compacted through a process whose accuracy is controlled by the user.1.1

In this paper, a new efficient methodology for building block layout is presented by using synthesis placement and compaction. The synthesis placement part of the methodology is based on a formal language called GEOMETRIA. The compaction part is based on geometric reshapings (gs) of blocks and the merging of the communication channels. Both reshaping and merging follow the VLSI regulations for legal layout placement and improve the overall functional performance of the integrated system, by reducing the average length of the connection lines and the size of the occupied chip area by retaining the functionality and the neighboring relations of the blocks. The main goal of the blocks' geometric reshaping is minimization of the wasted area (or dead space among the blocks) called "open holes". The channels merging process of compaction is based on the legal overlapping of the blocks' communication channels by reducing the layout placement at the local and global routing.