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Jeffrey D. Hirschberg

dblp:14/4168 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2005
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 50% Hardware accelerators and domain-specific architectures · 38% Parallel and multicore computing · 12%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
bioinformatics accelerator
0.112005
The UCSC Kestrel Parallel Processor · IEEE Trans. Parallel Distributed Syst. 2005
Processor architecture and microarchitecture › SIMD
SIMD processor
0.112005
The UCSC Kestrel Parallel Processor · IEEE Trans. Parallel Distributed Syst. 2005
Processor architecture and microarchitecture
SIMD
0.012005
The UCSC Kestrel Parallel Processor · IEEE Trans. Parallel Distributed Syst. 2005
Parallel and multicore computing › data parallelism
SIMD vectorization
0.012005
The UCSC Kestrel Parallel Processor · IEEE Trans. Parallel Distributed Syst. 2005

Methods — techniques the papers use, named apart from their topics

performance analysis · 0.1architectural design · 0.1
YearPublicationVenuePosition
2005 The UCSC Kestrel Parallel Processor
abstract
The architectural landscape of high-performance computing stretches from superscalar uniprocessor to explicitly parallel systems, to dedicated hardware implementations of algorithms. Single-purpose hardware can achieve the highest performance and uniprocessors can be the most programmable. Between these extremes, programmable and reconfigurable architectures provide a wide range of choice in flexibility, programmability, computational density, and performance. The UCSC Kestrel parallel processor strives to attain single-purpose performance while maintaining user programmability. Kestrel is a single-instruction stream, multiple-data stream (SIMD) parallel processor with a 512-element linear array of 8-bit processing elements. The system design focuses on efficient high-throughput DNA and protein sequence analysis, but its programmability enables high performance on computational chemistry, image processing, machine learning, and other applications. The Kestrel system has had unexpected longevity in its utility due to a careful design and analysis process. Experience with the system leads to the conclusion that programmable SIMD architectures can excel in both programmability and performance. This work presents the architecture, implementation, applications, and observations of the Kestrel project at the University of California at Santa Cruz.
Andrea Di Blas, David M. Dahle, Mark Diekhans, Leslie Grate, Jeffrey D. Hirschberg, Kevin Karplus, Hansjörg Keller, Mark Kendrick, Francisco J. Mesa-Martinez, David Pease, Eric Rice, Angela Schultz, Don Speck, Richard Hughey
IEEE Trans. Parallel Distributed Syst.5
1996 Kestrel: A Programmable Array for Sequence Analysis
abstract
Kestrel is a programmable linear systolic array processor designed for sequence analysis. Among other features, Kestrel includes an 8-bit word, a single-cycle add-and-minimize instruction, and efficient communication using systolic shared registers. This paper describes Kestrel's functional units in detail, and examines each of their effects on system performance. With prototypes currently in progress, we expect to complete a full Kestrel array, with between 512 and 1024 processing elements, by 1997.
Jeffrey D. Hirschberg, Richard Hughey, Kevin Karplus, Don Speck
ASAP1