A set of algorithms that implement a technique called Supercompaction is described for two-dimensional compaction layouts. The algorithms minimize a one-dimensional objective function (pitch) by moving objects in the layout in two dimensions. The objective function can be monotonically reduced to a locally minimal value, greatly simplifying search. The algorithms can change the layout by simple motion of components or by automatic jog introduction. Experiments shows that: (1) the number of iterations required to reach a locally optimal layout is very small; (2) the time per iteration is competitive with other compaction techniques; (3) supercompacted layouts are smaller in pitch and area than those produced by existing one-dimensional algorithms; and (4) the results of supercompaction are more predictable than those of existing one-dimensional methods.>

In this paper, we take a hard look at scheduling considerations in computing arrays. A simple sufficient condition is developed for determining whether a computing array can be pipelined. If the array cannot be pipelined in the form given, the condition also indicates the direction in which to proceed to make it pipelineable. The overall framework and methodology take a good part of the load off the logical architect of the array, and make the translation from the logical to the physical architecture a mechanical process.

In this paper, we present a systematic way to describe the logical architecture of the system implementing a given algorithm by means of an extended block diagram, and develop a standard notation to describe each block. We then show a technique for correctly transforming a block diagram into a physical circuit description by introducing the notion of time into the block diagram, and describe an algorithm that optimally assigns a limited number of hardware modules to all the function blocks in the diagram.

Digital processing of Synthetic Aperture Radar (SAR) data requires very large amounts of computation. In this paper we consider the feasibility of a VLSI implementation of the azimuth compression part of a real-time SAR processor. The area/size requirements of such a processor are evaluated by means of a prototype design. Two processing architectures are compared in terms of their suitability for VLSI implementation.