Software-Defined Networking (SDN) leverages centralized control to enhance network flexibility, programmability, and resource management. However, this centralization also makes it susceptible to Distributed Denial of Service (DDoS) attacks. In this attack, both compromised hosts and malicious third-party applications flood the controller with fake requests, causing network disruptions and potential failures. Existing literature lacks a comprehensive solution that effectively addresses both compromised host-based and application-layer DDoS attacks. Additionally, there is no mitigation mechanism capable of blocking malicious traffic directly at its source. To address this limitation, we propose DDoSBlocker which is a protocol-independent and lightweight DDoS defense mechanism against multi-layer DDoS attacks in SDN. It consists of three essential modules. The first module identifies the source points of compromised hosts responsible for DDoS attacks by leveraging time-based mapping technique integrated with machine learning technique. The second module detects malicious third-party applications by analyzing their application IDs using a machine learning approach with six novel features. Finally, the last module implements a mitigation strategy that effectively blocks malicious traffic at its source, ensuring minimal impact on legitimate network operations. DDoSBlocker is deployed in the Floodlight controller, and its effectiveness is assessed across multiple network scenarios. Our experimental results demonstrate that DDoSBlocker successfully detects and mitigates various types of DDoS attacks while achieving a 25–53% reduction in False Positive Rate (FPR) compared to existing approaches.

Heterogeneity in the cell population of cancer tissues poses many challenges in cancer diagnosis and treatment. Studying the heterogeneity in cell populations from gene expression measurement data in the context of cancer research is a problem of paramount importance. In addition, reducing the computation time of the algorithms that deal with high volumes of data has its obvious merits. Parallelizable models using Markov chain Monte Carlo methods are typically slow. This article presents a novel, computationally efficient, and parallelizable model to analyze heterogeneity in cancer tissues using GPUs. Because our model is parallelizable, the input data size does not affect the computation time much, provided the hardware resources are not exhausted. Our model uses qPCR (quantitative polymerase chain reaction) gene expression measurements to study heterogeneity in cancer tissue. We compute the cell proportion breakup by accelerating variational methods on a GPU. We test this model on synthetic and real-world gene expression data collected from fibroblasts and compare the performance of our algorithm with those of Markov chain Monte Carlo and expectation maximization. Our new model is computationally less complex and faster than existing Bayesian models for estimating cancer tissue heterogeneity.

Solid-state drives (SSDs) are fast emerging as the primary choice for data storage in diverse domains. However, data protection against ransomware attacks on such storage devices is a crucial challenge. A recent research work proposed an In-SSD ransomware protection mechanism to improve SSD data security. The SSD flash translation layer (FTL), which consists of an address mapping, garbage collection, and wear leveling components, is inherently the most complex part of an SSD controller. The In-SSD ransomware protection mechanism adds a new component to the FTL, making the FTL design more complex. The new component interacts with almost all other units of FTL for recovery from a ransomware attack. Such a design would naturally require rigorous verification, which is the focus of this article. In this work, we discuss the derivation of a set of security properties related to protection from ransomware that covers the security requirements and the design; we next prove such properties using symbolic model checking.

In a cancer study, the heterogeneous nature of a cell population creates a lot of challenges. Efficient determination of the compositional breakup of a cell population, from gene expression measurements, is critical to the success in a cancer study. This paper presents a new model for analyzing heterogeneity in cancer tissue using Markov chain Monte Carlo (MCMC) algorithms; we aim to compute the proportion wise breakup of the cell population on a GPU. We also show that the model computation time does not depend on the input data size, because the computation required to estimate the compositional breakup are parallelized. This model uses qPCR (quantitative polymerase chain reaction) gene expression data to determine compositional breakup in the heterogeneous cell population. We test this model on synthetic data and real-world data collected from fibroblasts. We also show how well this model scales to hundreds of gene expression data.

Exploiting data locality in GPGPUs is critical for efficiently using the smaller data caches and handling the memory bottleneck problem. This paper proposes a thread block-centric locality analysis, which identifies the locality among the thread blocks (TBs) in terms of a number of common data references. In LocalityGuru, we seek to employ a detailed just-in-time (JIT) compilation analysis of the static memory accesses in the source code and derive the mapping between the threads and data indices at kernel-launch-time. Our locality analysis technique can be employed at multiple granularities such as threads, warps, and thread blocks in a GPU Kernel. This information can be leveraged to help make smarter decisions for locality-aware data-partition, memory page data placement, cache management, and scheduling in single-GPU and multi-GPU systems.The results of the LocalityGuru PTX analyzer are then validated by comparing with the Locality graph obtained through profiling. Since the entire analysis is carried out by the compiler before the kernel launch time, it does not introduce any timing overhead to the kernel execution time.

Modern NVMe SSDs are widely deployed in diverse domains due to characteristics like high performance, robustness, and energy efficiency. It has been observed that the impact of interference among the concurrently running workloads on their overall response time differs significantly in these devices, which leads to unfairness. Workload intensity is a dominant factor influencing the interference. Prior works use a threshold value to characterize a workload as high-intensity or low-intensity; this type of characterization has drawbacks due to lack of information about the degree of low- or high-intensity.

The leakage power dissipation has become one of the major concerns with technology scaling. The GPGPU register file has grown in size over last decade in order to support the parallel execution of thousands of threads. Given that each thread has its own dedicated set of physical registers, these registers remain idle when corresponding threads go for long latency operation. Existing research shows that the leakage energy consumption of the register file can be reduced by under volting the idle registers to a data-retentive low-leakage voltage (Drowsy Voltage) to ensure that the data is not lost while not in use. In this paper, we develop a realistic model for determining the wake-up time of registers from various under-volting and power gating modes. Next, we propose a hybrid energy saving technique where a combination of power-gating and under-volting can be used to save optimum energy depending on the idle period of the registers with a negligible performance penalty. Our simulation shows that the hybrid energy-saving technique results in 94% leakage energy savings in register files on an average when compared with the conventional clock gating technique and 9% higher leakage energy saving compared to the state-of-art technique.

Formal modeling and analysis of a victim DRAM cache has already been discussed in the existing literature. These works use interacting state machines to model states and transitions of a victim DRAM cache. In this work, we address model-code conformance between a formal model of the victim DRAM cache and a simulator obtained from it. Our work focuses on a two-step approach to validate a DRAM cache implementation. In the first step, we use a technique based on it Feedback-Directed Random Testing to reverse engineer the state models from the execution traces. This process helps us to match the implementation with the state machines associated with the formal model and to verify some of the state-based properties. In the second step, we instrument the implementation with monitors and validate the liveness and safety properties (during run-time) which have been proved earlier in the formal model.

NAND flash memory has become the de facto standard for several non-volatile storages used in commercial and mission-critical applications. The advanced operations supported by NAND flash memory contribute to device performance and also influence the design of some of the crucial mechanisms of the flash memory device controller. In this research, we consider a recent ONFI standard i.e. ONFI-3.2 and successfully model the NAND flash memory device with the advanced operations in addition to many basic operations in contrast to the existing research works. We encode all the properties obtained from the standard in LTL and proved those using symbolic model checking. Our modeling approach simplifies the state machines and reduces resource requirements while capturing the essential information needed to verify the requirement based properties.

The emerging Die-stacking technology enables DRAM to be used as a cache to break the “Memory Wall” problem. Recent studies have proposed to use DRAM as a victim cache in both CPU and GPU memory hierarchies to improve performance. DRAM caches are large in size and, hence, when realized as a victim cache, non-inclusive design is preferred. This non-inclusive design adds significant differences to the conventional DRAM cache design in terms of its probe, fill, and writeback policies. Design and verification of a victim DRAM cache can be much more complex than that of a conventional DRAM cache. Hence, without rigorous modeling and formal verification, ensuring the correctness of such a system can be difficult. The major focus of this work is to show how formal modeling is applied to design and verify a victim DRAM cache. In this approach, we identify the agents in the victim DRAM cache design and model them in terms of interacting state machines. We derive a set of properties from the specifications of a victim cache and encode them using Linear Temporal Logic. The properties are then proven using symbolic and bounded model checking. Finally, we discuss how these properties are related to the dataflow paths in a victim DRAM cache.

GPGPUs are now commonly used as co-processors of CPUs for the computation of data parallel and throughputintensive algorithms. However, memory available in GPGPUs is limited for many applications of interest; there is a continuous demand for increased memory of such applications. Several techniques like multi-steaming or pinned memory are frequently employed to mitigate these issues to some extent. However, these techniques either suffer from latency overhead or increase programming complexity. GPUdmm uses GPU DRAM as a cache of CPU; key problems in this design are inefficient memory access data-path and tag access overhead. In this context, we present CAMO, a novel cache memory organization for GPGPUs which addresses the limitations of pinned memory technique and GPUdmm. First, it uses GPU DRAM as a victim cache of LLC that improves the performance by delivering data faster to the SMs. Second, it uses ATCache, a CPU based DRAM cache tag management technique. ATCache reduces the number of DRAM cache accesses. We implement CAMO within the GPGPU-Sim framework and show that its average performance - when compared with pinned memory - increases by a factor of 1.87x and the peak performance growth being 4.67x. In addition, CAMO outperforms GPUdmm on an average by a factor of 15.9% and maximum speedup by a factor of 80%.

Die-stacking technology enables the use of a high density DRAM as a cache. Major processor vendors have recently started using these stacked DRAM modules as the last level cache of their products. These stacked DRAM modules provide high bandwidth with relatively low latency compared to the off-package DRAM modules. Recent studies on DRAM caches propose several variants to optimize performance and power of the systems. However, none of the existing works discuss its design and verification aspect. DRAM cache controller (DCC) design is significantly complex in comparison to a conventional DRAM-based main memory controller. This is because it involves controlling both the timing aspect of DRAM system as well as the functional aspect of cache. Therefore, without rigorous modeling and verification of such designs, it would be difficult to ensure correctness. In the current research, we focus on the design and verification issues of DCC. We select a common variant of DRAM cache and build a formal model of its controller in terms of interacting state machines; we term the common variant as the baseline and its model as the base model. We then verify safety, liveness, and timing properties of this variant using model checking. Next, we demonstrate how the formal models and the associated properties of other variants of DCCs can be derived from the base model in a systematic way. Analyzing the individual DRAM cache variations, we observe that most of the variants exhibit product-line characteristics.

State models are widely used as specification or design artifacts and form the basis of various analysis techniques. In this paper, we make use of the advances in the area of random test generation to propose a novel approach to infer state models of black-box components from their executions. We also present an implementation and the results of applying our approach on a number of examples.

The Simulink/Stateflow (SL/SF) modeling framework is widely used in industry for the development of control applications. However, such models are not amenable to formal reasoning. Controllers can also be designed using formal specification languages. Such designs can be formally verified, but the models do not explicitly represent control or data flow information. In this paper, we discuss RRM diagrams (RRMDs), a new modelling notation which incorporates the benefits of these two formalisms. RRMDs are graphical formal models and they also support incremental formal development. We have used synchronising state machines to encode RRMDs. We have also developed a prototype tool which translates RRMDs automatically to SL/SF designs.

The current approaches for regression test selection of embedded programs are usually based on data- and control-dependency analyses, often augmented with human reasoning. Existing techniques do not take into account additional execution dependencies which may exist among code elements in such programs due to features such as tasks, task deadlines, task precedences, and intertask communications. In this context, we propose a model-based regression test selection technique for such programs. Our technique first constructs a graph model of the program; the proposed graph model has been designed to capture several characteristics of embedded programs, such as task precedence order, priority, intertask communication, timers, exceptions and interrupt handlers, which we consider important for regression-test selection. Our regression test selection technique selects test cases based on an analysis of the constructed graph model. We have implemented our technique to realize a prototype tool. The experimental results obtained using this tool show that, on average, our approach selects about 28.33% more regression test cases than those selected by a traditional approach. We observed that, on average, 36.36% of the fault-revealing test cases were overlooked by the existing regression test selection technique.

Simulink/Stateflow (SL/SF) is the primary modeling notation for the development of control systems in automotive and aerospace industries. In model based testing, test cases derived from a design model are used to show model-code conformance. Safety standards such as ISO 26262 recommend model based testing to show the conformance of a software with the corresponding model. From our experiments with various test generation techniques, we have observed that their coverage capabilities are complementary in nature. With this observation in mind, we have developed a new tool called SmartTestGen which integrates different test generation techniques. In this paper, we discuss SmartTestGen and the different test generation techniques utilized - random testing, constraint solving, model checking and heuristics. We experimented with 20 production-quality SL/SF models and compared the performance of our tool with that of two prominent commercial tools.

SUMMARY This paper is concerned with test case generation from Simulink/Stateflow (SL/SF) models with a focus on coverage of SF model elements. Coverage of the SF component in a model is a difficult task because of two primary reasons: (i) the SF component itself may lie deep in the SL/SF model in which case, inputs have to pass through a complex chain of SL blocks to reach the SF block and (ii) nonlinear constraints in the model are difficult to solve using constraint solvers. Hierarchy and parallelism in the SF model add further complexity to the problem. The existing approaches flatten such SF elements, and generate test cases from the flattened finite state machines. Handling of issues (i) and (ii) has already been discussed in earlier research. In this paper, we present a method of covering SF components, which does not require to flatten any hierarchy or parallelism in the components. This not only makes the test case generation problem efficient but also addresses the problem of scalability. We have implemented this method and performed a number of medium‐sized case studies. The results show improved performance over the results obtained by some commercial tools. Copyright © 2011 John Wiley & Sons, Ltd.

Automotive architectures today consist of up to 100 electronic control units (ECUs) that communicate via one or more FlexRay and CAN buses. Multiple control applications - like cruise control, brake control, etc. are specified as Simulink/Stateflow models, from which code is generated and mapped onto the different ECUs. In addition, scheduling policies and parameters, both for the ECUs and the buses, need to be specified. Code generation/optimization from the Simulink/Stateflow models, task partitioning and mapping decisions, as well as the parameters chosen for the schedulers all of these impact the execution times and timing behaviour of the control tasks and control messages. These in turn affect control performance, such as stability and steady-/transient-state behaviour. This paper discusses different aspects of this multi-layered design flow and the associated research challenges. The emphasis is on model-based code generation, analysis, testing and verification of control software for automotive architectures, as well as on architecture or platform configuration to ensure that the required control performance requirements are satisfied.

The Simulink/Stateflow (SL/SF) environment from Math-works is becoming the de facto standard in industry for model based development of embedded control systems. Many commercial tools are available in the market for test case generation from SL/SF designs; however, we have observed that these tools do not achieve satisfactory coverage in cases when designs involve nonlinear blocks and Stateflow blocks occur deep inside the Simulink blocks.

The communication environment surrounding our daily experience is increasingly characterized by mobile devices that can exchange multimedia information and provide access to various services of complex nature. The trend is now clear that future consumer computing experience will be based on multiple pervasive communication devices and services, where navigability, context-sensitivity, adaptability and ubiquity are key characteristics. Several issues have been studied, models and methodologies proposed, and tools and systems implemented. However, we look at the foundation, where some of the most relevant issues probably are a formal model of context-awareness and context-dependency. In this paper, we discuss a formal foundation and software engineering techniques for mobile context-aware and context-dependent service derivation and application development, emphasizing the relationships between context and system.

Assertions had their origin in program verification. For the systems developed in industry, construction of assertions and their use in showing program correctness is a near-impossible task. However, they can be used to show that some key properties are satisfied during program execution. We first present a survey of the special roles that assertions can play in object oriented software construction. We then analyse such assertions by relating them to the case study of an automatic surveillance system. In particular, we address the following two issues: What types of assertions can be used most effectively in the context of object oriented software? How can you discover them and where should they be placed? During maintenance, both the design and the software are continuously changed. These changes can mean that the original assertions, if present, are no longer valid for the new software. Can we automatically derive assertions for the changed software?.

Abstract Software processes vary across organizations and over time. Managing this process diversity is a delicate balancing act between creative, healthy diversity and chaos. In this paper, we examine a particular aspect of this issue, namely some relationships between diversity in software processes, software evolution and the quality of software products and processes. Our main contribution is to distinguish between two broad kinds of process diversity, which we call latitudinal and longitudinal process diversity. To illustrate the differences between these two, we examine the case of a medium‐sized system (50 000 lines of C++ code) which has undergone major changes during its lifetime of 10 years. The software was originally developed by an individual academic using a research‐oriented process to develop a standalone proof‐of‐concept system. In a current multi‐team project, involving three industrial and three academic partners, the software has been adapted for integration as a subsystem of a near‐market product. We suggest ways in which the observed process diversity seems to be linked to a change in the software's propensity for evolution, and we discuss the impact of this on both product and process quality. Copyright © 2003 John Wiley & Sons, Ltd.

It has been claimed that dynamic prediction models can be used to help project managers make more accurate estimates than static prediction models. However, such a claim needs to be validated so that project managers can use dynamic models with confidence. In this paper we discuss an experiment we conducted in an academic environment that compared a dynamic model using Bayesian belief networks (BBN) with a static model involving the COCOMO and Akiyama models. The results from this experiment in fact validate the above claim. However we suggest replication of this experiment in order to increase confidence to our results.

The motivation behind the idea of product focused process improvement is to make a process improvement program address certain product quality features in an explicit manner. The PROFES methodology (http://www.profes.org) describes such an improvement program through the notion of a PPD (Product-Process Dependency) repository. The typed generic process model (TGPM) (Satpathy et al., 2000) is a parametric template which relates each process attribute with the way it is likely to affect the quality of the intermediate as well as the end products. TGPM could be instantiated to generate process models for individual processes. This paper shows how the TGPM and the PROFES methodology both address product quality in a similar manner and how they could be complementary to each other as regards to product focused process improvement.

Unregulated evolution of software often leads to software ageing which not only makes the product difficult to maintain but also breaks the consistency between design and implementation. In such a case, it may become necessary to re-engineer the software so that it becomes maintainable again. In this paper we present the case study of the reengineering of the People Tracking subsystem of a surveillance system written in C++. We discuss the problems, the challenges and the approaches taken, and we show how the re-engineered product is now better maintainable. We also discuss the generation of the relevant artefacts - from requirement document through to design document.